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Found 11 results

  1. Hello, my friends, i am new here and it is my first project. This project will be my BSC. I have to make next: 1. Make USB CAM interfacing on System Level using systemC... My diagrams are shown in the post. I need to capture the photo using a USB CAM. After that, the picture needs to be stored in some memory. After that the image processing logic (In my case, the logic needs to have the photo (stored in memory) as its input, the idea is just to decrease the photo size (pixels) and the output is the result (decreased size picture)), after that the result of processing needs to be stored in memory too. After that i have to choose... in easier way i will use some photo viewer to see the result, in more difficult way i will use HDMI in order to see my result on the HDMI enabled monitor. My plan is making it on System Level using coding, HLS,IP integrator, SDK for some software. 2.If SystemLevel work great i need to make it on RTL, IP level using pure HDL. I will use Vivado. I am not sure for now what i need to modify from SystemC to IP level (For now, i think just Image processing logic). 3.IP verification using QuestaSim. I have a question: 1. Has someone done something similar? Can you help me, like as give me some good literature or example (For now i am focusing on USB interfacing, i have been searching about this about few days, but without results..., I have read a book (SystemC "From Ground up")). 2. All suggestions are welcome Best regards!
  2. Dear Experts, I want to implement XAPP1167 OpenCV HLS Xilinx project which mainly shows the edge at the output video. In the ZYBO hdmi demo project, I have added this custom IP between the interface of video in and AXI4 stream to VDMA. Initially, I got the error message says, "Bus interface property TDATA_NUM_BYTES does not match". Then I added axis_subset_converter_0 which allows me to downgrades TDATA width from 3 to 2 byte and successfully validated the updated designed. I also able to generate bit stream but the design does not fulfil the timing requirements. I am getting total negative slack -64.679 nano seconds. Please have a look into my design and give some possible suggestions. Regarding the IP core, I am sending a colour image of 1920*1080. Any kind of information regarding adding HLS ip into zybo hdmi demo project will be very helpful for me. thanks.. Shuvo
  3. PhDev

    Vivado HLS

    Hi, Do you have any experience of using Vivado High Level Synthesis, HLS? Today I use VHDL and C/C++ in microblaze. I am interested in testing HLS but don't know if it is worth spending time on that. Is it easy to get things running using HLS? What are the main pro/cons using HLS instead of VHDL/Verilog? Are the tools mature? Best regards
  4. the error are : note: candidate function template not viable: requires 3 arguments, but 5 were provided void dut_mmult_accel_core ( sorce/main.cpp:645:2: error: no matching function for call to 'dut_mmult_accel_core' dut_mmult_accel_core <float, 60, 1*60, 4, 5, 5>(in_stream, out_stream, predict_label1_hw_trig,precision1_hw_trig,prob_estimates_t1_hw_trig); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ `dut_mmult_accel_core <float, 60, 1*60, 4, 5, 5>(in_stream, out_stream, predict_label1_hw_trig,precision1_hw_trig,prob_estimates_t1_hw_trig);` where (predict_label1_hw_trig,precision1_hw_trig,prob_estimates_t1_hw_trig):output ``` template <typename T, int DIM1,int DIM2,int DIMa,int DIMb,int DIMc,int DIMd,int DIMe,int DIMf, int SIZE, int U, int TI, int TD> void dut_mmult_accel_core ( AXI_VAL in_stream[SIZE], AXI_VAL out_stream[3*SIZE], //volatile ap_uint<1> *hw_trig) volatile ap_uint<1> *predict_label1_hw_trig; volatile ap_uint<1> *precision1_hw_trig; volatile ap_uint<1> *prob_estimates_t1_hw; { // Map ports to Vivado HLS interfaces #pragma HLS INTERFACE ap_fifo port=in_stream #pragma HLS INTERFACE ap_fifo port=out_stream // Map HLS ports to AXI interfaces #pragma HLS RESOURCE variable=in_stream core=AXIS metadata="-bus_bundle INPUT_STREAM" #pragma HLS RESOURCE variable=out_stream core=AXIS metadata="-bus_bundle OUTPUT_STREAM" #pragma HLS RESOURCE variable=return core=AXI4LiteS metadata="-bus_bundle CONTROL_BUS" ap_uint<1> logic_zero = 0; ap_uint<1> logic_one = 1; T LabelS [DIM1][DIM2]; T out predict_label1[DIMa][DIMb]; T out precision1[DIMc][DIMd]; T out prob_estimates_t1[DIMe][DIMf]; *predict_label1_trig = logic_zero; *precision1_trig = logic_zero; *prob_estimates_t1_trig = logic_zero; assert(sizeof(T)*8 == 32); *predict_label1_trig = logic_one; *precision1_trig = logic_one; *prob_estimates_t1_trig = logic_one; ```
  5. Hello, I have a Arty-Z7-20 board and got the hdmi_in demo working on it. I need to process the incoming hdmi stream and I found that doing it as an application on Zynq is too slow because pixel accesses are required. I would like to use the OpenCV functions in HLS to do this. I wrote the following program in HLS - #include <hls_video.h> void video_resize(hls::stream< ap_axiu<24,1,1,1> > &video_in, hls::stream< ap_axiu<24,1,1,1> > &video_out) { #pragma HLS INTERFACE axis port=video_in bundle=INPUT_STREAM #pragma HLS INTERFACE axis port=video_out bundle=OUTPUT_STREAM hls::Mat<1080, 1920, HLS_8UC3> src; hls::Mat<1080, 1920, HLS_8UC3> dst; #pragma HLS dataflow hls::AXIvideo2Mat(video_in, src); hls::Scale(src, dst, 2.0, 0.0); //Simple processing hls::Mat2AXIvideo(dst, video_out); } My questions are - 1) Where in the demo block design should I connect this? (a) Between the video-to-axi4-stream ip and the axi-vdma ip (b) Add 1 more axi-vdma IP with both read and write channels and connect to it (c) Some better alternative? 2) In HLS, this design was synthesized with a clock constraint of 6.7 ns, so it meets the HDMI clock constraint of 148.5 MHz. However, in IP Integrator, a default value of 100 MHz is taken and I am unable to change this. What is the solution? 3) Is there any Digilent reference design/demo that already has HLS OpenCV IP integrated into the block design? Xilinx provides XAPP1167, but this only compiles on 2014.4 version which I don't have. I don't know how to upgrade the design to the current version. I might be asking too much, but any help is appreciated. Thanks, Rajat Rao
  6. Hi, Currently I'm working with micorblaze and Kintex 7 board, for Pseudo_random bit sequence (PRBS) function. I have created HLS IP (PRBS), integrated IP with vivado and exported it to SDK. But in SDK, i am getting only "Single bit" value instead of sequence of random bits. Please anyone guide me. What`s wrong in my coding? Need help from anyone. I need to get non-stop stream of random bits out of the IP and to display on Tera Terminal through XSDK. Hls Source code #include <stdint.h> #include <stdio.h> #include "ap_cint.h" int PRBS_prj(int bit) { #pragma HLS INTERFACE s_axilite port=return bundle=a int start_state = 0xCD; int lfsr = start_state; unsigned period = 0; do { /* taps: 3, 2 and 1 ; feedback polynomial: x^3 + x^2 + 1 */ bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 4) ) & 1; printf("%d", bit); lfsr = (lfsr >> 1) | (bit << 7); ++period; } while (lfsr != start_state); return bit; } or int main(void) { static int lfsr = 0x3425u; unsigned int mask = 0xF0; int bit; /* Must be 16bit to allow bit<<15 later in the code */ //taps: 16 14 13 11; feedback polynomial: x^16 + x^14 + x^13 + x^11 + 1 bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5) ) & 1; lfsr = (lfsr >> 1) | (bit << 15); for (mask = 0xF0; mask; mask >>= 1) putchar('0' + !!(lfsr & mask)); return lfsr; }
  7. Hello there, This time i have a very simple design in HLS which takes in a 3d matrix, multiplies with a constant and gives output. It works for [64][64][64] matrix perfectly, but not for [128][128][128] matrix. Again I get the segmentation fault. Can somebody help me to know what fundamentally going wrong.. Thanks for your halp in advance. i have attached my design files here: core.cpp core.h core_test.cpp
  8. HI there, I have a zed board. Developing a design in HLS for algorithmic acceleration. When I run the c-simulation for my design in HLS , it is not run showing the following error: But when i do c-synthesis it synthesizes the design with synthesis report, where in under latency and interval I see question marks: '?' why this happens and how do i understand this behavior? How can i get it corrected? Thaks in advance
  9. Hi experts, If i use trigonometric(sin or cos) or math functions (pow, floor, ceil ) in HLS with fixed point design it gives me error: what is the workaround? Thanks in advance. mlem_csim.log gravity_csim.log
  10. shashi

    c simulation error in HLS

    Hi there, I get this error when I run the C simulation in HLS to implement on zed board. I know that this error occurs when classes or class member functions are set as the top-level for synthesis. But i am not able to figure out where exactly i am going wrong. Can someone guide me here.?
  11. Hi every one, I want to a IP CORE for face detection that created by HLS. According to OpenCV function for face detection (Cascade Classifier), I found similar function in “hls/hls_video_haar.h” in to “hls_video.h” library, But I don’t know How can I use these function for face detection. Please help me about these topic. Best wishes.