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Found 22 results

  1. I wrote a simple vhdl design to test the gpio. Background story is that Im working on a more complex design which I rewrote two times until I come to the point that my electrical setup (which is quite simple) could be the problem. Stupid me! EDIT: I use the Arty board file and the xdc file provided by Digilent! Code of the simple test gpio design: library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity io_test is generic( d_width : integer := 16; --width of each data word size : integer := 64; --number of data words the memory can store a_width : integer := 6 -- width of the adress bus ); port ( i_clk : in std_logic ; btn : in std_logic; led : out std_logic; led_2 : out std_logic; test_io : out std_logic_vector ((d_width + a_width + 1) downto 0) ); end io_test; architecture Behavioral of io_test is signal clk_counter : integer := 0; signal clk_1hz : std_logic := '0'; signal test_io_buf : std_logic_vector((d_width + a_width + 1) downto 0) := "000000000000000000000001"; signal insr : std_logic_vector(2 downto 0); signal led_buf : std_logic := '0'; begin btn_async : process(i_clk) begin if(rising_edge(i_clk)) then insr <= insr(1 downto 0) & btn; end if; end process; io_test : process (i_clk) begin if(rising_edge(i_clk) and i_clk ='1') then if (insr(2 downto 1) = "01") then test_io_buf <= test_io_buf(d_width + a_width downto 0) & '0'; led_buf <= not led_buf; end if; end if; end process; test_io <= test_io_buf; led <= btn; led_2 <= led_buf; end Behavioral; If I simulate the file with: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; entity test_of_ram is end test_of_ram; architecture Behavioral of test_of_ram is component io_test port( i_clk : in std_logic ; btn : in std_logic; test_io : out std_logic_vector ((16 + 6 + 1) downto 0); led : out std_logic ); end component; ------------------------------------------------------------------------------ -- Signals and Types ------------------------------------------------------------------------------ constant OFFSET : integer := 15; signal btn, clk : std_logic := '1'; signal led : std_logic; signal test_io : std_logic_vector ((16 + 6 + 1) downto 0); begin dev_to_test: io_test port map( btn => btn, test_io => test_io, i_clk => clk, led => led ); ------------------------------------------------------------------------------ -- Clock Stimulus ------------------------------------------------------------------------------ clk_stim : process begin wait for 5 ns; clk <= not clk; end process ; -- clk_stim ------------------------------------------------------------------------------ -- IO Stimulus ------------------------------------------------------------------------------ io : process variable cnt: integer := 0; begin for I in 1 to 16 loop wait for 100ns; btn <= not btn; end loop; end process ; -- read_write_stim end Behavioral; I get the following result: Which is exactly what I want. But led_2 never lights up and only gpio0 stays on 3.3V (measured with multimeter) xdc file: ## LEDs set_property -dict {PACKAGE_PIN H5 IOSTANDARD LVCMOS33} [get_ports led] set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports led_2 ]; #IO_25_35 Sch=led[5] #set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { o_led[1] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6] #set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7] ## Buttons set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn }]; #IO_L6N_T0_VREF_16 Sch=btn[0] #set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1] #set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2] #set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3] ## Clock signal set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports i_clk] create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk] #set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] ## ChipKit Outer Digital Header set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS33} [get_ports {test_io[0]}] set_property -dict {PACKAGE_PIN U16 IOSTANDARD LVCMOS33} [get_ports {test_io[1]}] set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports {test_io[2]}] set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS33} [get_ports {test_io[3]}] set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports {test_io[4]}] set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports {test_io[5]}] set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS33} [get_ports {test_io[6]}] set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { test_io[7] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7] set_property -dict {PACKAGE_PIN N15 IOSTANDARD LVCMOS33} [get_ports {test_io[8]}] set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS33} [get_ports {test_io[9]}] set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS33} [get_ports {test_io[10]}] set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS33} [get_ports {test_io[11]}] set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports {test_io[12]}] set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS33} [get_ports {test_io[13]}] ## ChipKit Inner Digital Header set_property -dict {PACKAGE_PIN U11 IOSTANDARD LVCMOS33} [get_ports {test_io[14]}] set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS33} [get_ports {test_io[15]}] set_property -dict {PACKAGE_PIN M13 IOSTANDARD LVCMOS33} [get_ports {test_io[16]}] #set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ram_addr[1] }]; #IO_25_14 Sch=ck_io[29] set_property -dict {PACKAGE_PIN R11 IOSTANDARD LVCMOS33} [get_ports {test_io[17]}] set_property -dict {PACKAGE_PIN R13 IOSTANDARD LVCMOS33} [get_ports {test_io[18]}] set_property -dict {PACKAGE_PIN R15 IOSTANDARD LVCMOS33} [get_ports {test_io[19]}] set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports {test_io[20]}] #set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { test_io[21] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34] #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { test_io[22] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35] set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports test_io[21]] #set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS33} [get_ports {test_io[7]}] set_property -dict {PACKAGE_PIN T18 IOSTANDARD LVCMOS33} [get_ports {test_io[22]}] set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {test_io[23]}] #set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io40 }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40] #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io41 }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41]
  2. Hello everyone. I am learning UART communication with Nexys video board. Using only IP integrator, I succeed to 'turn on the LEDs with SWs' and now, I tried to use custom counter module by Verilog. module clock_divider( input clk, input [4:0]key, output reg [7:0]led ); //we will need one register to keep the clock count number; reg [22:0] count; always @(posedge clk) // judge the clk rise edge; if (key) begin // if the key has been pressed, if(count==0) begin // then count value flip over to zero, then make led on or off led <= ~led; // in the always loop, it needs to use registers end count <= count +1; // add the count value until it flips over to zero end else begin // if there is no key to be pressed, init the led to off state; led <=0; count <=1; end endmodule and I included this module in IP design. and the errors were like below. before this errors, I connected slight different module~IP wiring , and the result was ' synthesis & implement succeed, Bitstream failed' I'm looking for some information on google, but hard to find out my problem. can you give me some hints or solution? Thank you for your kind answers, ...
  3. I am learning how to operate an FPGA, and I have to input a signal (which in itself is the output of a discriminator), and analyze it through a Basys3 FPGA. Looking at the available ports on the board, I'm guessing that it could be done using the Pmod ports, but even after hours of googling and going through the manuals, I failed to know which data ports to use, and how to read the signal after I've input it through the board. I've got references to some boards, in which GPIO ports are explicitly labelled, but I don't see any such labeling on the Basys3. So, it'd be really helpful if someone can provide me with any insight regarding this. Any other references or links would also be greatly appreciated. I've already gone through the basic tutorials (like lighting the led using the switch. I just want to know how to use the input ports, and analyze my signal. Thank You
  4. hello, i am planning to hookup the 4x4 pmodKEYPAD with ML605 FPGA LVDS I/O pins of vertex6 FPGA , anyone could you please suggest how to interface...also can LVDS pins can be used as GPIO?
  5. hello, I practice to use vivado 2018.2 to create two AXI GPIOs like the first picture. I could use C program to pass the ON/OFF from switchs to leds;however, the XGpio_DiscreteRead() is always blocked by gets() when i want to use gets() to get cmd,and write data to leds according cmd. The following is my C code.Please introduce me to solve the problem. Thank you a lot. #include "xparameters.h" #include "xgpio.h" #include <stdio.h> #include <stdlib.h> #include "sleep.h" int main(){ XGpio output,input; /* SW &LED Instance */ int button_data=0x00; int switch_data=0; int led_value = 0; int i=0; char cmd[4]; XGpio_Initialize(&output, XPAR_AXI_GPIO_1_DEVICE_ID); XGpio_SetDataDirection(&output, 1, 0x0); XGpio_Initialize(&input, XPAR_AXI_GPIO_0_DEVICE_ID); XGpio_SetDataDirection(&input, 1, 0xF); while(1) { i++; printf("This the %d time run the while loop\n\r",i); printf("Enter Command: \n\r"); gets(cmd); switch_data = XGpio_DiscreteRead(&input, 1); printf("switch_data = %d\n\r",switch_data); led_value = switch_data+1; XGpio_DiscreteWrite(&output, 1, led_value); printf("data wrtie over"); printf("=========================================="); usleep(20000); } return 0; }
  6. Hello, finally i was able to make a petalinux build with the BSP 2017.4 - so far, so good. Then i find out, which uio device is connected with the Arty-Z7-20 Buttons and switches. Both - the Buttons and also the Switches - are connected to one GPIO-IP-Core (Dual-Channel, all inputs). One AXI-GPIO has one base address and a dual channel GPIO has even only one base address. So the only way to address both channels is to use the base address offset for channel one and for channel two, isn't it? If i read channel one - which is assigned to the Buttons - then i can read the Buttons. If i read the channel two (Switches) - one code line later - then i got no result. So my questions is: What must i do to read the Arty-Z7-20 Switches (petalinux, BSP 2017.4)? Thank you...
  7. I am working on my biggest FPGA project as of so far. Ive previously completed USB RXD/TXD serial com FTDI, VGAPMOD graphics, BRAM circuits, Mouse/KB circuits, and of course LOGIC/PROCESSING. Now im embarking upon interfacing a Raspberry PI zero GPIO to ARTY PMOD connectors. The GOAL is that the PI will become a slave unit to the FPGA where RPI0 USB 2.0 devices, RAM, HDMI Graphics/Sound, and processing will be entirely controlled by the FPGA ARTY Board. Im planning on 1) 8/16bit INPUT BUS to the RPI0 and 1) 8/16bit OUTPUT BUS from the RPI0 with data on/off bus interrupt signals. FPGA send/receive processing seems pretty straight forward, where data control words interrupts and data signals work in tandem. My only seemingly weak point In the project is that im new to RPI programming using python, even with many years of education in programming, Ive only glanced over Python structure and syntax. Im just not 100% certain of how many of my native architectures in CS programming will carry over to python. Important areas Arrays, Code Strings, GPIO connectivity, sound/graphics, KB/Mouse handling, File/Folder Handling, are all new to me on a Raspbian/Linux PYTHON system, even with years of experience with JAVA. BASIC, C/C++, ASM/ML mainly for MS windows. Input suggestion and advice is welcome on any level. Regards, DC
  8. liwerfm

    Input pins GPIO

    Hello, I am trying to drive GPIO's 19 to 0, and trying to turn on the leds when a 3.3 voltage is applied in any of this pins, but it doesn't work u32 btn, led; XGpio gpio; XGpio_Initialize(&gpio, 0); init_platform(); XGpio_SetDataDirection(&gpio, 2, 0x0); //output leds XGpio_SetDataDirection(&gpio, 1, 0xFFFFFFFF); //input pins print("Start test\n\r"); while(1){ btn = XGpio_DiscreteRead(&gpio, 1); putnum(btn); print("\n\r"); if (btn!=0) // turn all LEDs on when a 3.3 voltage is applied in any input pin led = 0xFFFFFFFF; else led = 0x00000000; XGpio_DiscreteWrite(&gpio, 2, led); } The leds are always on and the terminal always print 3FFF I am using Arty7-35t, Vivado 2016.4.
  9. Hello, i made the following design: You can see two GPIO Ports: - GPIO_RGB_LED, 3 Bit, Output only - GPIO_SW, two data bits plus one interrupt bit (e.g. Input clk), this port should throw Interrupts into the Linux App. After i build that design with Vivado, i used petalinux to create a Linux image. Here you can see the "/dev"-Folder which contains the installed Drivers: You can see three GPIO-Drivers. Now my question: In former questions i ask for the Driver Support in Linux and how i can write or use them. You told me, that there is a simple way to access memory mapped ip-cores with the "uio"-Driver. First i was glad to see that the Drivers are automaticaly added to the image. But i'am missing the expected "uio"-Drivers. What must i do to get the "uio"-Drivers for my design with petalinux? Thank you...
  10. Hello, I create project on SDSoc 2015.4 using platform ( and I select Operating System is Linux because I use about image processing. but I want to access 4 LEDs on PL. Can I access the LED on PL? How to access GPIO (e.g. LEDs) on OS: Linux Previously I used OS: Standalone project. I can access by Xil_Out32(XPAR_AXI_GPIO_LED_BASEADDR, 0x2); but on Linux I can't. Thanks in advance
  11. I desperately want to connect three devices to a Raspberry Pi3 that has a single Pmod HAT Adapter fitted to it. The devices are all SPI types: Pmod AD1 Pmod ISNS20 Pmod TC1 I can only run 2x devices since ports JA(A) and JB(A) both support SPI, but JC(A) does not. Is stacking of Pmod HAT Adapters allowed or can I connect an SPI device directly to the open GPIO pins? I would greatly appreciate any advice! Even if NOPE is an answer...
  12. Hello, I was earlier able to flash LEDs on the Zybo 7010 board following the tutorials. However, I am currently trying to use the Zybo 7010 to flash LEDs which are external to the board. What I am looking at here is getting a constant voltage supply from one of the ports (maybe preferably the Xadc) to power the external LED circuit. I am having trouble getting a block design using the xadc_wiz_0 ip and the axi gpio with the zynq 7000 processor. Any information on this is greatly appreciated.
  13. Dear Experts I am using Petalinux 2015.4 and Zedboard. I am reading a GPIO which is supposed to go from 0 to 1 and in commandline, I can see that it happens. But when I execute it in the code, the value always remain 0 as initial value is 0. My code is as follows: int number=-1; unsigned char error = 0; int fd_done; //Export GPIO fd_done = open("/sys/class/gpio/export", O_WRONLY); if(fd_done < 0) { #if DEBUG_GPIOBit printf("ERROR:\tGPIO Export Failed\n\r"); #endif error=1; } write(fd_done,"903",3); close(fd_done); //Set GPIO as input fd_done = open("/sys/class/gpio/gpio903/direction", O_WRONLY); if(fd_done < 0) { #if DEBUG_GPIOBit printf("ERROR:\tGPIO Direction Failed\n\r"); #endif error=1; } write(fd_done,"in",2); close(fd_done); char value; fd_done = open("/sys/class/gpio/gpio903/value", O_WRONLY); lseek(fd_done, 0, SEEK_SET); read(fd_done, &value, 8); printf("Done Value: \t %d \n",value); close(fd_done); fd_done = open("/sys/class/gpio/unexport", O_WRONLY); write( fd_done,"903",3); close(fd_done); return number;
  14. Dear Experts I need help regarding interrupt handling using UIO. I am using Vivado 2015.4 and Petalinux 2015.4. The board used is Zedboard. I made the following vivado project attached as image. The interrupts from AXI and Fabric (PL-PS) are enabled. Afterwards i was able to export it as UIO and it shows in /dev as uio0. Now I implemented the following code by following this link: My code is as follows: /* * File: main.c * Author: fss * * Created on August 23, 2017, 12:35 PM */ #include <sys/mman.h> #include <stdio.h> #include <stdint.h> #include <stdlib.h> #include <poll.h> #include <fcntl.h> #include <errno.h> #define GPIO_DATA_OFFSET 0x00 #define GPIO_TRI_OFFSET 0x04 #define GPIO_DATA2_OFFSET 0x08 #define GPIO_TRI2_OFFSET 0x0C #define GPIO_GLOBAL_IRQ 0x11C #define GPIO_IRQ_CONTROL 0x128 #define GPIO_IRQ_STATUS 0x120 unsigned int get_memory_size(char *sysfs_path_file) { FILE *size_fp; unsigned int size; // open the file that describes the memory range size that is based on the // reg property of the node in the device tree size_fp = fopen(sysfs_path_file, "r"); if (size_fp == NULL) { printf("unable to open the uio size file\n"); exit(-1); } // get the size which is an ASCII string such as 0xXXXXXXXX and then be stop // using the file fscanf(size_fp, "0x%08X", &size); fclose(size_fp); return size; } void reg_write(void *reg_base, unsigned long offset, unsigned long value) { *((volatile unsigned long *)(reg_base + offset)) = value; } unsigned long reg_read(void *reg_base, unsigned long offset) { return *((volatile unsigned long *)(reg_base + offset)); } uint8_t wait_for_interrupt(int fd_int, void *gpio_ptr) { static unsigned int count = 0, bntd_flag = 0, bntu_flag = 0; int flag_end=0; int pending = 0; int reenable = 1; unsigned int reg; unsigned int value; // block (timeout for poll) on the file waiting for an interrupt struct pollfd fds = { .fd = fd_int, .events = POLLIN, }; int ret = poll(&fds, 1, 100); printf("ret is : %d\n", ret); if (ret >= 1) { read(fd_int, (void *)&reenable, sizeof(int)); // &reenable -> &pending // channel 1 reading value = reg_read(gpio_ptr, GPIO_DATA_OFFSET); if ((value & 0x00000001) != 0) { printf("Interrupt recieved"); } count++; usleep(50000); // anti rebond if(count == 10) flag_end = 1; // the interrupt occurred for the 1st GPIO channel so clear it reg = reg_read(gpio_ptr, GPIO_IRQ_STATUS); if (reg != 0) reg_write(gpio_ptr, GPIO_IRQ_STATUS, 1); // re-enable the interrupt in the interrupt controller thru the // the UIO subsystem now that it's been handled write(fd_int, (void *)&reenable, sizeof(int)); } return ret; } int main(void) { int fd = open("/dev/uio0", O_RDWR); if (fd < 0) { perror("open"); exit(EXIT_FAILURE); } int gpio_size = get_memory_size("/sys/class/uio/uio0/maps/map0/size"); /* mmap the UIO devices */ void * ptr_axi_gpio = mmap(NULL, gpio_size, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); while (1) { wait_for_interrupt(fd,ptr_axi_gpio); } close(fd); exit(EXIT_SUCCESS); } But the issue is that this code is not catching the interrupt. Kindly help me in this. Any suggestion/links are more than welcomed Regards
  15. Hi all! I'm currently thinking of purchasing the pynq-z1 board and hoping to set up CAN communication on it. I've read the documents regarding the PYNQ board ( but I wasn't able to conclude on whether I would need to purchase a PMOD with it to access a CAN peripheral. From what I understood, many of the peripherals are available through the PL via PMODs or an arduino. There was also a comment stating that peripherals such as Ethernet, USB and UART, are connected externally, while all other peripherals are connected internally or routed to PL pins. This confused me so my questions are: What do you mean by "connecting peripherals internally"? and would I need to purchase a PMOD and route my CAN controller to PMOD pins, in order to interface with CAN? (via overlays, I believe?). Just need some confirmation! I'm sorry if I'm asking something so basic, I'm fairly new to embedded development, especially with zynq chips but I'm keen to learn as I go! -Vin
  16. Hello, I created a block diagram that has a axi_gpio_0 block, as you can see in my image. Below is most of my constraint file. My diagram synthesizes, implements and generates a bitstream. I was able to get into SDK with no problems. I am stuck in SDK now. Goal: I am just trying to blink an LED (gpio_io_o[4]) using one of the the example code projects shown in system.mss file. I chose the "xgpio_example.c"; first on the list. The example code has these lines: #define LED 0x01 and #define LED_CHANNEL 1. This code should just simply blink an LED. I am not sure if LED_CHANNEL is channel "1", or what "LED_CHANNEL" means in the code. Using these original settings my LED did not blink or light up at all. Looking at my constraint file, you will see that I am using gpio_io_o[4] and gpio_io_o[5] for my LEDs, so I changed the first line to #define LED 0x04. This had no effect. I tried everything I could think of. For example, I tried making a change like this: #define LED_CHANNEL 4, but this had no effect. I tried many combinations of things. Using the oscilloscope, I looked at all of the pins on the PMOD connector, but nothing is active. I'm sure I programmed the FPGA and code correctly since the processes went smoothly. I'm trying to avoid using any IP blocks other than the built in axi_gpio blocks. Those IP blocks from example code do not TEACH us anything and are rather useless in that regard. I've looked all over, but cannot find a working version of "BLINKY" code (which is fairly standard in MCU and Microprocessor examples). Can someone please point out a decent GPIO tutorial that actually works? Here is a sample of the code: XGpio_SetDataDirection(&Gpio, LED_CHANNEL, ~LED); The "LED_CHANNEL" AND ~LED parameters are confusing. Why is LED inverted? For example, if LED = 0x01, then ~LED = 0xfffffffe. Why? Thank you, Richard V My constraint file: # LEDs set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o[4] }]; #led[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1] set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o[5] }]; #led[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2] Here are my other GPIO bits: #OLED set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { spi_0_ss_io[0] }]; #CS #IO_L5N_T0_D07_14 Sch=ja[1] set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { spi_0_io0_io }]; #MOSI #IO_L4N_T0_D05_14 Sch=ja[2] set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { spi_0_io1_io }]; #MISO #IO_L9P_T1_DQS_14 Sch=ja[3] set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { spi_0_sck_io }]; #SCK #IO_L8P_T1_D11_14 Sch=ja[4] set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o[0] }]; #DC #IO_L5P_T0_D06_14 Sch=ja[7] set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o[1] }]; #RES #IO_L4P_T0_D04_14 Sch=ja[8] set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o[2] }]; #VBAT #IO_L6N_T0_D08_VREF_14 Sch=ja[9] set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { gpio_io_o[3] }]; #VDDC #IO_L8N_T1_D12_14 Sch=ja[10] This is an excerpt from the example code and was generated by SDK: #include "xparameters.h" #include "xgpio.h" /************************** Constant Definitions *****************************/ #define LED 0x01 /* Assumes bit 0 of GPIO is connected to an LED */ /* The following constants map to the XPAR parameters created in the * xparameters.h file. They are defined here such that a user can easily * change all the needed parameters in one place. */ #define GPIO_EXAMPLE_DEVICE_ID XPAR_GPIO_0_DEVICE_ID /* * The following constant is used to wait after an LED is turned on to make * sure that it is visible to the human eye. This constant might need to be * tuned for faster or slower processor speeds. */ #define LED_DELAY 1000000 /* * The following constant is used to determine which channel of the GPIO is * used for the LED if there are 2 channels supported. */ #define LED_CHANNEL 1 /**************************** Type Definitions *******************************/ * The purpose of this function is to illustrate how to use the GPIO * driver to turn on and off an LED.* * @param None ** @return XST_FAILURE to indicate that the GPIO Initialization had * failed. ** @note This function will not return if the test is running. * ******************************************************************************/ int main(void) { u32 Data; int Status; volatile int Delay; /* Initialize the GPIO driver */ Status = XGpio_Initialize(&Gpio, GPIO_EXAMPLE_DEVICE_ID); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* Set the direction for all signals as inputs except the LED output */ XGpio_SetDataDirection(&Gpio, LED_CHANNEL, ~LED); design_spi_oled.pdf
  17. Hello ! We are designing a high-speed bus on a PCB interfacing the Arduino/Chipkit GPIO pins onboard the PYNQ-Z1. Inorder to maximize the signal integrity parameters, we would like to optimize the trace lengths in our board based on the trace information and the layer stackup details of the PYNQ board. It would be really kind if someone from Digilent could share this valuable information to assist our optimization. Regards, r4d
  18. Hi all I have a very simply UART TX/RX pair I have built in Verilog, and have been struggling to get them to function on the Arty Board. I can connect the two together to form a simple "echo" function, where any received RX data is immediately sent out on the TX module, but beyond that I can't correctly see the values I send to the Arty. I tried simply piping the received byte to the LEDs on the Arty board, but the values lit up do not correspond at all to the ones I expect. Sending the character string "AaA" does not make the ascii encodings for "A" and "a" appear on the LEDs. However, I do get the right characters echoed back to my PuTTY terminal. My code for the project can be found here: You'll need: rtl/uart_rx.v , rtl/uart_tx.v, rtl/impl_top.v and constraints/default.xdc to re-create the project. I'm using Vivado 2016.4 on Ubuntu 16.04. Thanks, Ben
  19. bino

    Connect my IP module

    HI ! First : I'm a new in FPGA development For my experiments, I designed an IP module (in Verilog), which takes 3 inputs (clk, rst, walk[7:0]) and drives in funny way leds. Decided, that it's too much for this to use AXI memory mapped interface and used for control signal only 8-bit vector. My question is : can I use AXI GPIO with 8 bits output and connect only it's output vector to my IP's "walk" ? As I tried, the default value from GPIO works, but couldn't drive this value from the SDK at the address of the AXI GPIO ? Or may be some more clean way ? Sorry, forgot : I test the design on Zybo.... Thank you in advance ! design_1.pdf
  20. I'm very confused as to why I can't get 3 GPIO's to work as desired. I'm trying to program 3 external shift registers. The control lines are Clk, Latch, Output Enable and Data In. I've implemented a ~240Hz timer to cycle between 4 16-bit values to be sent to the shift registers. Everything works except the 3 data inputs. The actual failure is the bit shifting and mask of each of the 16-bits of the 3 data in variables. I'm including my code and an analyzer trace (uc32 pins directly to a Saleae logic analyzer). I'd appreciate anyone that could shed some light. Thanks! Test.pde /* To turn on any given channel, set the pin LOW. To turn off, set the pin HIGH. The higher the analogWrite level, the lower the brightness. This example code is in the public domain. */ #define __32MX340F512H__ 1 #include <p32xxxx.h> #include <plib.h> #define CLK 0x0400 // D10 #define Ou1 0x0080 // D07 #define Ou2 0x0040 // D06 #define Ou3 0x0020 // D05 #define OE 0x0010 // D04 #define LE 0x0008 // D03 #define E0 0x0040 // G06 #define E1 0x0080 // G07 #define E2 0x0100 // G08 #define E3 0x0040 // F06 #define INDCTR 0x0800 // D11 #define CTR1 0x0020 // F5 #define CTR0 0x0010 // F4 #define PIN_CLK 8 #define PIN_Ou1 37 #define PIN_Ou2 36 #define PIN_Ou3 34 #define PIN_OE 10 #define PIN_LE 9 #define PIN_E0 13 #define PIN_E1 12 #define PIN_E2 11 #define PIN_E3 38 #define PIN_CTR1 40 #define PIN_CTR0 39 #define PIN_INDCTR 35 #define CPU_HZ 80000000 #define TICKS_PER_SECOND (CPU_HZ / 2) #define Tx_ON 0x8000 #define Tx_PS_1_8 (3 << 4) #define Tx_SOURCE_INT 0 volatile uint32_t counter = 0; volatile uint32_t intHit = 0; volatile uint32_t eCount = 0; volatile uint32_t OutA1[4] = { 0xaaaa, 0x5555, 0x9999, 0x6666 }; volatile uint32_t OutA2[4] = { 0x5555, 0x9999, 0x6666, 0xaaaa }; volatile uint32_t OutA3[4] = { 0x9999, 0x6666, 0xaaaa, 0x5555 }; /* Define the Interrupt Service Routine (ISR) */ void __attribute__((interrupt)) myISR() { ++counter; if ( counter == 4 ) counter = 0; intHit = 1; if ( counter & 0x01 ) LATFSET = CTR0; else LATFCLR = CTR0; if ( counter & 0x02 ) LATFSET = CTR1; else LATFCLR = CTR1; LATDSET = INDCTR; _nop(); LATDCLR = INDCTR; clearIntFlag(_TIMER_3_IRQ); } /* start_timer_3 */ void start_timer_3( uint32_t frequency ) { uint32_t period; period = TICKS_PER_SECOND / frequency; T3CONCLR = Tx_ON; /* Turn the timer off */ T3CON = Tx_PS_1_8; /* Set the prescaler */ TMR3 = 0; /* Clear the counter */ PR3 = period; /* Set the period */ T3CONSET = Tx_ON; /* Turn the timer on */ } void setup() { // Initialize serial communications: Serial.begin(115200); Serial.println("hello"); // Set all used outputs to open-drain ODCDSET = CLK | Ou1 | Ou2 | Ou3 | OE | LE | INDCTR; ODCFSET = E3 | CTR1 | CTR0; ODCGSET = E0 | E1 | E2; // Set all used outputs to a low LATDCLR = CLK | Ou1 | Ou2 | Ou3 | OE | LE | INDCTR; LATFCLR = E3 | CTR1 | CTR0; LATGCLR = E0 | E1 | E2; // Set all Analogue pins to digitial AD1PCFG = 0xffff; // Set LED Control outputs to normal TTL, not open-drain ODCDCLR = CLK | Ou1 | Ou2 | Ou3 | OE | LE | INDCTR; ODCFCLR = E3 | CTR1 | CTR0; ODCGCLR = E0 | E1 | E2; // set LED control pins as outputs TRISDCLR = CLK | Ou1 | Ou2 | Ou3 | OE | LE | INDCTR; TRISFCLR = E3 | CTR1 | CTR0; TRISGCLR = E0 | E1 | E2; // Disable the interrupt-on-change for IO pins CNCONCLR = 0xe000; // Set OE to high LATDSET = OE; counter = 8; intHit = 0; start_timer_3( 60 * 4 ); /* 240 Hz */ setIntVector( _TIMER_3_VECTOR, myISR ); setIntPriority( _TIMER_3_VECTOR, 4, 0 ); clearIntFlag( _TIMER_3_IRQ ); setIntEnable( _TIMER_3_IRQ ); } void loop() { int i, j; int to1, to2, to3; if ( intHit ) { eCount = counter & 0x03; /* Make sure CLK and LE are low */ digitalWrite( PIN_CLK, LOW ); digitalWrite( PIN_LE, LOW ); /* Make sure OE is hi */ digitalWrite( PIN_OE, HIGH ); /* Prepare the Out Data lines by setting them LOW */ digitalWrite( PIN_Ou1, LOW ); digitalWrite( PIN_Ou2, LOW ); digitalWrite( PIN_Ou3, LOW ); to1 = OutA1[eCount]; to2 = OutA2[eCount]; to3 = OutA3[eCount]; for ( i = 0; i < 16; i++ ) { /* Test Red */ if ( to1 & 0x01 ) { digitalWrite( PIN_Ou1, HIGH ); } /* Test Green */ if ( to2 & 0x01 ) { digitalWrite( PIN_Ou2, HIGH ); } /* Test Blue */ if ( to3 & 0x01 ) { digitalWrite( PIN_Ou3, HIGH ); } /* Toggle CLK */ digitalWrite( PIN_CLK, HIGH ); digitalWrite( PIN_CLK, LOW ); to1 = to1 >> 1; to2 = to2 >> 1; to3 = to3 >> 1; } /* Toggle LE, then set OE low */ digitalWrite( PIN_LE, HIGH ); digitalWrite( PIN_LE, LOW ); digitalWrite( PIN_OE, LOW ); digitalWrite( PIN_E0, LOW ); digitalWrite( PIN_E1, LOW ); digitalWrite( PIN_E2, LOW ); digitalWrite( PIN_E3, LOW ); switch ( eCount ) { case 0: digitalWrite( PIN_E0, HIGH ); break; case 1: digitalWrite( PIN_E1, HIGH ); break; case 2: digitalWrite( PIN_E2, HIGH ); break; case 3: digitalWrite( PIN_E3, HIGH ); break; default: break; } intHit = 0; } }
  21. Hello everybody, I have some issue regarding using XADC and GPIO on Zybo board. Here is the situation: When I use just GPIO, everything works fine and proper. Also when I used XADC alone everything works good. But when I use both GPIO and XADC, I get some error in generating bit-stream which shows that incompatible IO bank because of nature of “GPIO” and A/D converter. Here is my block-diagram: and here is the error message. do you guys have any idea or experience regarding this issue? thank you in advance.
  22. asmao

    PMOD as GPIO

    Hello, I'm currently using a Nexys 4 board and I would like to serially output and receive data. I was wondering if this could be done through a PMOD port? If so, how? Inside of my HDL design (I'm using Vivado 2014.2 and my HDL is in verilog) I'm asserting various PMOD ports yet whenever I try to measure the outputs I got nothing. My HDL looks something like this:assign JC1 = 1, JC2 = 0; Both JC1 and JC2 measure to 0. I've also tried the alternative names listed in the schematics (K2 and E7) as well as other PMOD interfaces. If I can't use the PMOD ports in this fashion, I was hoping to hear any suggestions? Thanks,Alvin