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Found 6 results

  1. Hi, I'm relatively new to using Vivado with the Digilent boards. I have an Arty Z7-20 and started using it with Vivado 2019.1. I want to move on to Vivado 2020.1. When I originally installed 2019.1 I downloaded the Digilent vivado-library-v2019.1 from here There does not seem to be a library v2020.1, v2019.1 seems to be the latest. Can I use library v2019.1 with Vivado 2020.1 or is there another way to achieve this? Thanks for your help!
  2. Hi, I am using Arty 7 to generate clock with different frequency. I wanted to save this data in my PC .since baud rate is 115200 and i am generating clock with 5MHZ ie at Rate of 5mbps. here speed of generation and data transfer are not same,speed of data transfer is much less than generation. please suggest me how can I save the data which i am genereting at same time.should I use ethernet for It?
  3. I'm working with ARTY-A7 FPGA board and ADEPT v2.19.2 in Windows 10. At first, the system often lost contact with the board, but after reinstalling digilent.adept.system_v2.19.2, the connection was restored. Now reinstalling no longer helps. What can be a reason?
  4. ozden.erdinc

    Vivado AXI QUAD SPI

    Hello, I am dealing with Vivado Ip cores. I want to design SPı interfaces by using AXI QUAD SPI in microblaze. Unfortunately, when I designed my cores and when I generated bitstream Imy designed failed. Also I added DDR3 because I tought that maybe Microblaze caches are not enough for SPI. Before the generating bitstream I get these critical warning in the validation session. When I ignore these warning as we know that my block designs failed. Can you help me this issue? I am really dealing with with it . I would really appreciate it.
  5. I'm stumped and have been pouring through the posts in these forums over the last couple of days but can't quite get to a solution. I know this has sort of been beaten to take it easy on me. I'm trying to get the Arty A7-100T board to boot from SPI flash on power-up. I'll try to go in the order of which I've configured things as concisely as possible...any insight or help is much appreciated. IP block in Vivado is customized as shown in image below. In addition, I've connected 'ext_spi_clk' to a 50MHz clock generated by the clocking wizard. Bitstream generates successfully and design is exported to SDK. I've run numerous applications out of BRAM and DDR3 via the normal microblaze bootloop (i.e. no flash) so I know the system is configured correctly to some degree. I've tried this both WITH and WITHOUT a compressed bitstream as noted in the tutorial here: I generated the BSP with xilifs library v5.12 and set 'serial_flash_family' to 5. I then created a user application with a modified linker script to run out of DDR3. I verified this works just fine in the standard microblaze bootlop as noted above. I generated the 'srec_spi_bootloader' application. I originally set the memory location to 0x00C00000, but have since used 0x00300000. Complied the application with no issues. I then generated a bitstream as indicated in the tutorial with the 'srec_spi_bootloader.elf' set to initialize in Block RAM. Followed the steps for programming flash - first loaded the user application at the memory offset that matches the compiled 'srec_spi_bootloader' application (so 0x00300000). Then programmed the generated bitstream at offset 0x0. Originally, I had the wrong memory part selected and have had difficulty finding any documentation that points to the updated part. Ultimately just read the letters on the actual part itself and found that 's25f128sxxxxxx0-spi-x1_x2_x4' worked. So that's what I've been using. After programming and power cycling, I see the DONE LED illuminate but nothing happens. There's been some tweaks to the process here and there, but this seems to be the most convincing order of operations I've been able to find on the web. As an interesting side note, I can load the flash memory with the application at 0x00300000 and run the 'srec_spi_bootloader' out of the microblaze bootloop when it's set to initialize in Block RAM and it loads the application just fine. It's just when I add the step of writing the full bitstream to offset 0x0 that it fails to actually run the application on power-up, despite the fact the green DONE LED illuminates. Any thoughts???? 💡💡💡
  6. gsandy


    Vivado 2017.2 Windows 10 - I am a Vivado newbie I am trying to use the Arty board for some prototyping, I am trying to make my own new Block Design to instantiate in my new project, I grabbed the ethernet-lite reference design, I upgraded all IP. Added my new blocks, and generated. I am getting issues with the MIG, I checked the pinout of the symbols and it seems correct to match my axi_mem controller M0. I tried to re-customize the MIG_7series IP, the pinout seems correct against the reference design board.prj. . I checked the datasheet of the reference design and entered everything the same. I generated the block design selected Synthesis option as global : here are my errors: Block Design (6 errors): set_property -name {CONFIG.BOARD_MIG_PARAM} -value {ddr3_sdram} -objects [get_bd_cells mig_7series_0] [filemgmt 56-285] srcscanner execution failed with return code -1073741511. [filemgmt 56-285] srcscanner execution failed with return code -1073741511. [filemgmt 56-285] srcscanner execution failed with return code -1073741511. [filemgmt 56-285] srcscanner execution failed with return code -1073741511. If I ignore them and try to move forward I get errors in my other project about the MIG. Maybe I am missing something basic - looking for suggestion/solution/approach? Glenn