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Found 56 results

  1. Hi, I'm trying to boot a linux OS ( Ubuntu core armhf ) on Zybo board. I have done the following steps: 1. Create a project in Vivado 2017.2, a project consist of a Zynq and just one custom IP core, a led controller just to turn on and of the 4 leds on board. 2. I have successfully generated the bitstream and exported the hdf in SDK. 3. In SDK I have created a project for build the fsbl successfully 4. I have built u-boot ( git clone from xilinx repo on github ) just changing the zynq_common.h file to load just the kernel and the devicetree ( not the uramdisk because I would like to put the rootfs on sd card 2nd partition ) 5. I have built the kernel ( always from xilinx github ) using the zybo_zynq_defconfig as configuration and I have successfully generated the uImage 6. I have prepared a ubuntucorearmhf rootfs 7. I have packaged into BOOT.BIN file the fsbl, bitstream and u-boot 8. I have used the devicetree generator from xilinx github to generate my devicetree ( files attached ), with modified bootargs properly ( I hope ) 9. As you can see there is no PHY into pcw.dtsi or zynq-7000.dtsi so I have added that into a file called ethernet.dts ( made by me ) including the system-top.dts just to leave the auto-generated devicetree without modification. 10. I put the BOOT.BIN , uImage and devicetree.dtb ( compilation of ethernet.dts ) into the 1st partition of my sdcard, the rootfs into 2nd 11. At boot time the system boots without problem but it says that there is no PHY for ethernet and if I do an ifconfig the eth0 interface is absent. I have done a mistake on binding the PHY for realtek ethernet controller?? Another step I have tried is to use the BOOT.BIN and the image.ub provided by Digilent on zybo bsp 2015.4 (Digilent-Zybo-Linux-BD-v2015.4) and like this the PHY has been found and I can see the eth0 interface. I have also tried to understand the difference between my devicetree and the Petalinux one ( see .txt file ) without success. I have tried to use your zybo_base_system project instead of a clean project from scratch with same results. I have finally tried this , a project found on github where a guy boot Linaro ( I have done it with Ubuntu core ) using as start I think your zybo_base_system but with 3.18 kernel instead of 4.9 kernel and Vivado 2015.4 instead of Vivado 2017.2 . Thanks in advance. Michele ethernet.dts pcw.dtsi system-top.dts zynq-7000.dtsi gem0_node_petalinux_bsp.txt
  2. Monics

    Ethernet shield

    I am looking at using the Digilent modules together with Labview LINX (Makerhub), and I need a setup with ethernet connection to Labview/LINX. Digilent have retired the 410-211, Network Shield... but will I be able to use the Pmod NIC100 (together with max32 or uC32) and get support for ethernet interface through LINX....?Br,Martin Christiansen.
  3. Hi, I have the Zynq 7000 board (Z-7010). I'm trying to build a Vhdl Program that sends and basic Ethernet Frame throw the RJ45 onboard interface. I'm trying the Intr_Dma example to learn how to use the controllers on the PS. My block design is simply one block of Zynq7 Processing system with eth0 and UART1 enabled Exported the hardware to SDK and imported the example of emacps "xemacps_example_intr_dma.c". Run the program will show the following message from UART: "Entering into main() Error setup phy loopback" Debugging the program and I found the problem is inside function EmacPsUtilEnterLoopback of xemacps_example_util.c This function is to set the PHY chip to loopback mode. However, This functions only works for Marvell and TI chip. according to this great blog, this should work: i'v tried troubleshooting this problem,i'v added the fallowing lines:(to the "EmacPsUtilEnterLoopback" function) printf("%d\n",PhyIdentity); printf("%d\n",PHY_ID_MARVELL); printf("%d\n",PHY_ID_TI); the output is: Entering into main() 28 321 8192 Error setup phy loopback Therefor the realtec phy has PhyIdentity of 28, marvell phy is 321 and Ti phy is 8192. i'v tried changing the following lines: if (PhyIdentity == 28) { printf("phy is Marvell\n"); Status = EmacPsUtilMarvellPhyLoopback(EmacPsInstancePtr, Speed, PhyAddr); } after it didnt work, i've tried this lines: if (PhyIdentity == 28) { printf("phy is TI\n"); Status = EmacPsUtilTiPhyLoopback(EmacPsInstancePtr, Speed, PhyAddr); Nothing works. where can i find the relevant code? Thanks, David
  4. Hello, I have the Zynq 7000 board (Z-7010). I'm trying to build a Vhdl Program that sends and basic Ethernet Frame throw the RJ45 onboard interface. so far i'v constructed the Frame itself according to the Ethernet IEEE 802.3 standard, now i see there are Gmii and Rgmii Interface and a builtin Phy controller but i cant understand how to use them all. Is there a simple example of such a program? - I use the 2017.1 Vivado and the Z-7010 Board. Thanks.
  5. I have a ZYBO Board working fine with linux3.18. I have tested UART, I2C and Ethernet using linux3.18. But I needed to update my linux to 4.9, now ethernet cannot be configured. when I give ifcofig -a lo Link encap:Local Loopback LOOPBACK MTU:65536 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1 RX bytes:0 (0.0 B ) TX bytes:0 (0.0 B ) sit0 Link encap:IPv6-in-IPv4 NOARP MTU:1480 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1 RX bytes:0 (0.0 B ) TX bytes:0 (0.0 B ) It lists lo and sit0 and no eth0. I have searched web for a solution, but could not get anything useful. an someone help?
  6. Turn your Nexys Video board into something useful for hardware development by adding the IO capabilities of another FPGA board. In this project the other board is a Digilent Spartan 3A Starter board. But it has a lot of resources that make it useful for a variety of projects needing an FPGA. The "magic" is supplied by those wonderful Ethernet PHY modems. Release 3 offers two target boards, Gigabit and 100 Mbps designs. Check it out even if all you want to do is connect any two FPGA boards with Ethernet capability.
  7. I followed the ARTY Microblaze server tutorial and was able to get it working. However I noticed that it does not use any input or output delay constraints. I was trying to understand how it is being designed so that these constraints are not needed as well as how to add the constraints so I can check the timing of those timing paths On receive side: If I am reading the PHY datasheet correctly the RXD data line transitions are centered at the falling edge of the 25 MHz RX_CLK with but possibly varying from 10ns to 30ns after the rising edge of the clock. a quarter period of the clock.So if I understand this correctly the constraints would be for each pin something like: set_input_delay -max 30 -clock [get_clocks rx_clock] [get_ports RXD[1]] set_input_delay -min 10 -clock [get_clocks rx_clock] [get_ports RXD[0]] Is this the correct way to constrain these? The Ethernetlite MAC in the reference design appears to handle the design by: 1. Delay the RXD data inputs with a ZHOLD_DELAY block. 2. Put the RX_CLK is put onto a global clock buffer 3. latch the output of the ZHOLD_DELAY with the global clock into IOB FFs on the rising edge of the clk. Is these a reason that this would be guaranteed to work without the clock constraint? Any comments would be much appreciated Thanks!
  8. A UDP echo-server design uses on-board Ethernet port to create a data-link between FPGA board Nexys 4 DDR and MatLAB. Echo-server is capable of reception and transmission data packets using ARP and UDP/IP protocols. MAC address of FPGA board: 00:18:3e:01:ff:71 IP4 address of FPGA board: Port number of the board, used in the design, is 58210. The echo-server will reply back to any data server, which uses correct IP4 address and Port number of the board. MAC address of the board is made discoverable for the data server via ARP protocol. This echo-server design doesn't use any input or output FIFO's as elesticity buffers,both in- and outgoing data packets are parsed/assembled in parallel with Rx/Tx processes, which allows better resource utilisation at the price of, probably, more complex design architecture. Design is implemented in VHDL using ISE by Xilinx. Below there are the source files for the echo-server projects along with .m file to transmit/receive data using MatLAB. Figure "wireshark_capture" illustrates the data traffic between FPGA board and data server (MatLAB); Figure "TxRx_Error" compares transmitted data against the data received from the board. UDP echo-server manual.7z UDP echo-server.7z
  9. Hello all, I wish to receive 10 Mb of data through Ethernet using TCPIP protocol. I am newbie to LWIP so use Microblaze server demo code for reference. The problem i faced is i only able to receive 1460 bytes of data with echo server example code. I also added pbuf_copy_partial() function and specified pointer where data should be store but when i try to read data from pointer specified i am getting some garbage values. i also acknowledge packet reception but still i would't able to fix issue. i have also attach snapshot of code which i modified please suggest steps for data reception. Regards, Kumarkk
  10. Hello all! I'm trying to get an initial design up and running using the Nexys Video board. According to the specs listed for the board (both here and here), the board supports a 1Gbps ethernet speed, as well as 10/100 Mbps speeds. Looking at the spec for the RTL8211E ethernet chip that I found (is this the right one?), the 1Gbps interface requires 8 transmit data wires and 8 receive data wires working together at a 125 MHz clock. However, if you look at sheet 3 of the schematic for the Nexys Video, there aren't any 8 transmit or receive data wires connected at all, but rather a pair of 4-wire interfaces such as the 10/100Mbps speeds would require. Indeed, it appears as though the only interface connected is the 10/100Mbps interface. Can you confirm for me if this is the case, and if so ... might I suggest you update your description of the board to match the hardware on the board? If not, can you point me at the proper spec for the ethernet chip on board? Thanks! Dan
  11. Hello all, I'm trying to implement Microblaze server on Nexys 4 DDR. Design steps are provide on official website, i follow same procedure as mention on website but while generating Bitstream following error pop up and synthesis failed. please suggest possible errors in design and modification to be done to block diagram. I have attach snap of error message and Block diagram below. PFA, Thanks in Advance Regards, Kumar Khandagle.
  12. Hey I have followed the tutorial and I have the memory unit not enumerate correctly. It's block by the same name appears as a 2 port block. tutorial from nexys-4-ddr-getting-started-with-microblaze-servers found at I have the problem when I am adding the core "memory interface generator" in step 3.1 works and is per the figure, but the auto configuration of the block in step 4 doesn't appear to work because the figure in 4.2 looks different. I have started the project by downloading the Nexsys DDR board file and using that board file from section 1 as that would be the first thing that I checked. Please let me know where I might have gone wrong.
  13. Dear everybody. Thanks DIGILENT for their very nice demo on HDMI => VGA converter on ZYBO. I would like to use ZYBO to convert input HDMI image to VGA output and also write result to BRAM for later use. PS should also work in parallel reading those result out (from memory) and written to somewhere via Ethernet. As my understanding, the demo given by DIGILENT for HDMI => VGA converter uses no BRAM. I would like to know if some similar (to my purpose) demo is available and where on the design should I modify to achieve the above purpose. Best Regards,
  14. Hi, I want to test ethernet of my Zybo board. Referring to xapp1026,I got how to use sdk to build a project,however,is there any demo to test ethernet in detail? For example,how to test the communication between board and PC? If I use standalone mode,then what should I do ?and for embeded system? Regards, Sophia
  15. Are Analog Shield and Network Shields are compatible with the chipKIT Max32 at the same time? If so are there any special considerations? Thanks you for any help you can provide.
  16. eli

    Nexys4 Ethernet Example

    hi, i tried working with this tutorial on vivado 2016.2 . but when i'm trying to "Generate Bitstream" , i get an error and many warnings. can't figure why, anyone can help??
  17. Hi: I would like to implement an application in my fpga to communicate to the PC. I don't want to use the SDK, I prefer VHDL. So, I can generate a Xilinx LogiCORE Tri-Mode Ethernet MAC using Xilinx's Coregen, but I don't know how to connect it. For example, the global clock is 125Mhz, and the atlys only provides me a 100Mhz. Should I use a clock generator? Thanks.
  18. Following on from playing with Arty's 10/100 Ethernet Interface, I've got a Gigabit PHY working over the RGMII interface. It is really rough, as it doesn't yet handle the slower speeds correctly, but it is able to send 979 Mb/s to my laptop (not that my Laptop can keep up with it! Hopefully it will be of help to somebody who wants to get a lot of data off of their FPGA board without having the overhead of a CPU and full TCP/IP stack.
  19. How to send data from pc to nexys4 through ethernet, kindly guide me how to configure the ethernet protocol in nexys4. Urgent help required.
  20. Hello, I'm having a question about the address of the ZYBO ethernet phy on the mdio bus. The REF Manual says: What does that mean for the device tree? I've got the ethernet PHY working with the following device tree configuration: Where do I have to use the address 00001b? Greetings Heiner
  21. Hi, I am a beginner of ethernet design. I got a small project published on this website: . I have successfully updated MAC address, IP, etc... But I have no idea how to set constraint file in ISE. Through reading the Nexys 4 DDR manual, I guess I need an extra clkIn for this project to work on the board, so I created two clocks: one is for D5, CLKIN, 50MHz, and another is for the project, 20MHz. and I set the pin number in the project below. NET "clk" LOC = "E3" | IOSTANDARD = "LVCMOS33"; NET "clk" TNM_NET = sys_clk_pin; NET "Ethernet_TDp" LOC=A9 | IOSTANDARD=LVCMOS33; NET "Ethernet_TDm" LOC=C9 | IOSTANDARD=LVCMOS33; A9 is connected to MDIO, and C9 is connected to MDC. But I cannot see any data flow from PC to the board using the software provided by that website. Can anyone help me set the constraint file? Thank you!
  22. Hi everyone! I have a Nexys 3 board which I have used to implement some designs. Now I am working on a ethernet controller implementation to perform high speed data transfer between a PC and a FPGA (point to point). The Nexys 3 includes a 10/100 PHY IC, but I have to go up to a gigabit PHY to achieve my goals. Is there any kind of peripheral module with a gigabit PHY that I could use with my Nexys 3? Thanks in advance (and sorry for my english :))
  23. Hey guys! I followed the ''Embedded Linux hands-on tutorial'' to build and run Linux on my ZYBO board. I am trying to use the Ethernet but it seems does not work correctly. Here are some informations: I connect the board and my PC (ip adr: When I ping ZYBO from my PC I got "Destination host unreachable" and "request timed out". When I ping PC from ZYBO I got "sendto: Network is unreachable". I'm using Vivado 2014.2 under Ubuntu 14.04 and didn't do any changes in addition to the tutorial. So anyone can help me with this? Thanks a lot! Best regards, JImmy
  24. The HDMI2USB project aims develops affordable open hardware options to record and stream HD videos (from HDMI & DisplayPort sources) for conferences, meetings and user groups. Our current focus is on around custom gateware running on FPGA hardware, our gateware if fully open and can be found on github. The gateware allows for both full matrix functionality and capture via either USB or Ethernet. A control terminal is also available giving the computer complete management of all functionality. We have been using the Digilent Atlys as a prototyping platform and are investigating also supporting the Digilent Nexys Video. We are also developing our own hardware the Numato Opsis. As an open source project, we'd love help continuing to develop new features and functionality. We are actively seeking assistance: For video recording individuals+teams: Be an early adopter; get a board, start using it, report back to us with feedbackFor software/FPGA developers: Get involved in contributing code both to the capture software + FPGA stackOur aim is this becomes the defacto, incredibly affordable and easy to use video recording hardware for conferences, meetings and user groups worldwide. Find out more about HDMI2USB and why we’re doing this in ABOUT + FAQ
  25. From the album: - Firmware for capturing HDMI and DisplayPort via USB and Ethernet

    __ _____ __ _______ ___ __ _________ / // / _ \/ |/ / _/ |_ | / / / / __/ _ ) / _ / // / /|_/ // / / __/ / /_/ /\ \/ _ | /_//_/____/_/ /_/___/ /____/ \____/___/____/ alternative Copyright 2015 / EnjoyDigital [email protected] Alternative HDMI2USB gateware and firmware based on Migen/MiSoC [> Supported Boards ------------------ This firmware is supported on the following to boards; * Digilent Atlys - The original board used for HDMI2USB prototyping. Use `BOARD=atlys` with this board. * Numato Opsis The first production board made in conjunction with project. Use `BOARD=opsis` with this board.

    © MIT