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Found 54 results

  1. I setup my Nexys Video for the first time, and tried to setup an echo server using Vivado/SDK. I followed the following tutorial: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-getting-started-with-microblaze-servers/start When I go to generate a bitstream, I get the following error: [Common 17-69] Command Failed: This design contains one or more cells for which bitstream generation is not permitted: design_1_i/axi_ethernet_0_U0_mac_U0/tri_mode_ethernet_mac_i/bd_929b_mac_0_tri_mode_ethernet_mac_v9_0_12) If a new IP Core license was added, in order for the new license to be picked up, the current netlist needs to be updated by resetting and re-generating the IP output products before bitstream generation. The Nexys Video kit did not ship with a special Vivado license, am I required to purchase a license in order to use the Ethernet interface of my board?
  2. I am trying to run the xilinx example project xemacps_example_intr_dma (example) on baremetal zynq. I have tried copy pasting requisite files into a project and having it build by importing the example through the .mss file of the bsp. The hardware export is from a slightly modified version of the digilent getting started example using the master xdc file. The project compiles and loads but never enters the interrupt handler and gets hung at the while(!FramesRx) at line 819. My block diagram has a fixed io pin from the zynq ps running over to an external interface pin labeled fixed io which includes a subfield labeled mio. However the graphical ip-reconfig utility of the zynq ps has enet0 selected and the MIO configuration tab shows the MIO pins as 16..27 which I think are the correct pins for the enet PHY. A few questions come to mind: Presumably the phy chip has some specific configuration that has to occur that may not be a part of the rgmii specification, however the xilinx example makes no reference to configuring a board specific phy. I am missing this step and I need to write code to perform some config-init function specific to this chip? A brief look at the realtek phy however seems to show most options are configured using pull down resistors... Secondly, does the constraints file need to specify something about the ethernet pins? Because I find no mention of them in the master.xdc file but I also see no mention of the uart pins and the uart(through usb-to-uart chip) runs fine.
  3. Hello All, I am currently working on Nexys Video Ethernet. I want to transmit and recieve UDP packets between PC and Nexys Video FPGA . Is it possible to perform without Microblaze? How to send UDP Packets from PC to FPGA.?
  4. hi Now i'm using ZYBO. I tried to send data from ZYBO to PC by ethernet communication. I already succeed to check lwip echo server example. (https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start). what i want to do is sending XADC data from PS to pc by ethernet. So, can i do this by modifying echo server code? Is there any example about this? or other method? thanks.
  5. I am using Atlys board (Spartan-6). It has Marvell Alaska Tri-mode PHY (the 88E1111). I want to establish Ethernet connection (GMII- 10/100/1000 Mbps) which can dynamically switch between these speeds depending upon the type of network switch (10/100/1000 Mbps). Currently I am trying Address swap example generated by the trimac 4.6 core and it works fine with 1000 Mbps switch. When I change the switch (100 Mbps this time), address swap example doesn't transmit back the packet. I am using Colasoft packet builder and Wireshark to send and check the packets. On observing further, I found that there is a Multiplexer which is deciding the clock for either 100 or 1000 Mbps mode. The select line of this MUX is 'speedis10100_int'. I tied this signal (speedis10100_int) to an LED and found that this select line is not changing on changing the Switch (1000 to 100 Mbps). I further tried driving this select line of MUX manually by a Slide switch. Then I can observe the clock (output of MUX) changing from 125 Mhz to 25 Mhz (when i slide the switch and change the network switch to 100mbps). But still the address swap example doesn't work at 100 Mbps. Inputs of the MUX are 1) 125 Mhz generated by clock generator and, 2) mii_tx_clk (25 Mhz coming from PHY) Thanks in advance. Deepak Verma
  6. This is more of a tool than a project though I do hope that it inspires projects. In the course of developing some complex Ethernet projects involving boards from various vendors I had to develop a test tool to make development easier. I'm releasing a simpler version of that tool to help you develop your own Ethernet applications. You will also find it to be a handy tool for learning about using the Ethernet PHY on your FPGA board without the normal MAC/processor encumbrances. This submission has nothing to do with standard Ethernet or processor based Ethernet applications. The only downside for Version 1 is that you need a Digilent ATLYS board to serve as the test platform. [Edited] Not 4 hours have passed and I found a silly bug that mis-reported packet size. I've replaced the archive. I also forgot to add the teaser: Wed Oct 17 16:13:03 2018 test_interval_reg = 0x000000000100 >>> Starting test Payload Size = 65536 Total Number of TEST Packets sent = 60000 Total Number of TEST Packets received = 60000 Total Number of TEST Bytes sent = 3932160000 Total Number of TEST Bytes received = 3932160000 Total Number of Errors = 0 Total Number of PHY rxerr Events = 0 Total Duration of the test (in Seconds) = 31.585437952 Percentage Errors = 0.0 TEST packets sent per second = 1899.60956347 Tx Data Rate (Bytes/s) = 124492812.352 Rx Data Rate (Bytes/s) = 124492812.352 ETHERNET_PHY_TESTER_Release_V1A.zip
  7. hello, I need help with troubleshooting ethernet. when I use ifconfig, I get below information. eth0: flags=4099<UP,BROADCAST,MULTICAST> mtu 1500 inet 192.168.1.103 netmask 255.255.255.0 broadcast 192.168.1.255 ether 00:0a:35:00:1e:53 txqueuelen 1000 (Ethernet) RX packets 0 bytes 0 (0.0 B) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 0 bytes 0 (0.0 B) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 device interrupt 146 base 0xb000 lo: flags=73<UP,LOOPBACK,RUNNING> mtu 65536 inet 127.0.0.1 netmask 255.0.0.0 inet6 ::1 prefixlen 128 scopeid 0x10<host> loop txqueuelen 1 (Local Loopback) RX packets 39 bytes 4047 (3.9 KiB) RX errors 0 dropped 0 overruns 0 frame 0 TX packets 39 bytes 4047 (3.9 KiB) TX errors 0 dropped 0 overruns 0 carrier 0 collisions 0 when I ping 8.8.8.8, I get PING 8.8.8.8 (8.8.8.8) 56(84) bytes of data. From 192.168.1.103 icmp_seq=1 Destination Host Unreachable From 192.168.1.103 icmp_seq=2 Destination Host Unreachable ethernet setting in devicetree &gem0 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; I have tried changing some things in devicetree. but i am always getting the same error. ADDRCONF(NETDEV_UP): eth0: link is not ready thank you in advance. system-user.dtsi zynq-7000.dtsi
  8. Hello: I am unable to get Ethernet interface to work on Genesys-2 in my design which is migrated from a Xilinx board. I have a Microblaze based design that I am trying to port to Genesys-2 Board. This design is working on Xilinx KC705 evaluation board which uses the same Kintex-7 FPGA as Genesys-2. On this design I have Ethernet interface, DDR3 Interface and some other peripherals. We are using Linux for this design. This design was originally developed by another company and was used for evaluating their chip. It was developed on Xilinx evaluation board KC705. This company does not support any other evaluation board. I am hoping to get some help from forum experts to bring-up this design. For this design on Xilinx KC705 board after power up, downloading the bit file and running the SW from *.elf file we can open a PUTTY terminal and issue 'ifconfig' command to check whether the ethernet interface is up and which IP address it got. This works for Xilinx board. But the same does not work for Genesys-2 board, I can issue 'ifconfig' command but I don't see the ethernet interface active. I had looked for pinout differences and made changes accordingly. When I described the symptoms to the original authors of the design they said that because the PHY is different between the two boards I have to update the device tree. Below is the device tree from Xilinx KC705 design. Ethernet Device Tree axi_ethernet: ethernet@40e00000 { compatible = "xlnx,xps-ethernetlite-1.00.a"; device_type = "network"; interrupt-parent = <&axi_intc>; interrupts = <1 0>; local-mac-address = [00 0a 35 00 00 02]; phy-handle = <&phy0>; reg = <0x40e00000 0x2000>; xlnx,duplex = <0x1>; xlnx,include-global-buffers = <0x1>; xlnx,include-internal-loopback = <0x0>; xlnx,include-mdio = <0x1>; xlnx,rx-ping-pong = <0x1>; xlnx,s-axi-id-width = <0x1>; xlnx,select-xpm = <0x1>; xlnx,tx-ping-pong = <0x1>; xlnx,use-internal = <0x0>; axi_ethernet_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@7 { device_type = "ethernet-phy"; reg = <7>; }; }; }; PHY on Xilinx KC705 board is Marvell 88e1111. PHY on Genesys-2 is RealTek RTL8211E. The original authors of the design had suggested that at a minimum the line "reg = <7>;' should be changed for Genesys-2. My questions on the forum are below. 1) How should I modify the device tree for Ethernet for Genesys-2 board? 2) Does it seem that just changing the device tree for Ethernet will fix our issue? 3) Any suggestions on how to debug this issue? Thank you so much. Best regards,
  9. Hi I am trying to develop Ethernet transmission with Zybo Z7-10. I tried to add ports like eth_txctl to xdc file, but there is a critical warning I can't understand. You can see pictures in attachments, the ports in my module, the ports I connect pin with, also the project settings. I don't understand why vivado gives my critical warning that the pin is not valid. If I try the ports eth_rxctl and connects it with pin D13, there would't be any warnings. I attached the schematic link as well, where I found the pins and port. I really don't get it, for example, the ports eth_txctl and eth_rxctl are literally on the same block in schematic. According to the schematics, I connect ports and pins, how come there is one work and the other doesn't work? https://reference.digilentinc.com/_media/reference/programmable-logic/zybo-z7/zybo_z7_sch-public.pdf Thanks a lot
  10. Fields

    Arty and Ethernet

    Greetings! I am working with an Arty FPGA board in a personal project that involves the use of a computer and Ethernet to control the FPGA. As a first step, I want to manage the leds by using the computer. Probably a good choice will be to use a Tera Term terminal and manage the state of the leds with sentences like that: · Led 3 state ON · Led 2 state ON · Led 1 state OFF · Led 0 state OFF The problem is that so far I have never connected the FPGA to the computer using Ethernet before. I know that the best way to manage an Ethernet connection with the Arty is to use the Microblaze, and I have finished the “Getting started with Microblaze Servers” tutorial. That tutorial teaches how to implement an echo server but don´t teaches how to send orders from the computer to the FPGA by using Ethernet. Probably it is not as hard at it seems at first sight but it is the first time that I do something like this and I really don´t know how to start. What could be the best way to use the computer to connect and control the Arty? Is there any tutorial that explains how to remote control an FPGA board using the computer? I will appreciate any help and support I can get. Fields.
  11. Hi, I just got nexys video and was going down the list of out-of-box demo at the bottom of its reference manual : https://reference.digilentinc.com/reference/programmable-logic/nexys-video/reference-manual When I connect the ethernet cable, ACT/LINK/USER LEDs blink for a bit, then LINK/USER blink in sync indefinitely, but there's no IP address displayed on OLED screen, just shows 0.0.0.0 I tried checking things on my router side (Netgear), but there is no indication of the device in its logs. Are there any way to confirm that the ethernet is working properly?
  12. i want to recieve video packets from hdmi port and send it over ethernt RJ45 connector how it can be done with PYNQ board.
  13. Hello, Do you know if "Analog Shield: High-performance Add-on Board for the Arduino Uno" can also be used with "MCU Leonardo Ethernet 2 Arduino". Regards
  14. Hi, I am trying to run the lwIP echo server application project template from the Xilinx SDK on my PYNQ board. I have followed this tutorial for the Zybo FPGA board (which also contains the ZYNQ): https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start Everything works fine until the very last step, when I come to connect to the echo server using telnet. The PYNQ is telling my via serial comms that Board IP: 192.168.1.10 Netmask : 255.255.255.0 Gateway : 192.168.1.1 TCP echo server started @ port 7 So I followed the instructions in the above link to set up the ethernet connection on my Windows PC with the static IP address 192.168.1.11 using the given netmask. Unfortunately when I come to connect via telnet using Putty, it tells me that the host is unreachable. I have also tried using my Ubuntu PC but I get the same problem. I have tried debugging the echo server in the Xilinx SDK by setting a break point in the recv_callback() function, but it never seems to reach that part of the code, indicating that no packets are ever received from my PC. Does anybody have any idea what I could be doing wrong please? Thanks!
  15. anurag

    ethernet with cmod A7

    hello, i want to know whether or not it is possible to connect ethernet port to CMOD A7. as number of input output lines are restricted .if yes then how?
  16. Does anyone have the project for the initial project containing all peripheral interfacing?
  17. Hi, I'm trying the tutorial(https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq-server/start), but it doesn't work. I create a project in Vivado 2016.2 and SDK 2016.2. So, may I have the sample project in vivado and sdk 2016.2? Thanks, TM-san
  18. Hello, Need Help ASAP. I have a working code of FPGA (Altera DE2-115 ,cyclon-IV) for coin mining. Can I use that code on NetFPGA 1G CML for mining, if not what changes should I made in code? If yes, Then how can I connect it with Ethernet (PHY) of NetFPGA 1G CML? Will I need extra coding to connect it with Ethernet protocol? Thankx
  19. Hi, I'm trying to boot a linux OS ( Ubuntu core armhf ) on Zybo board. I have done the following steps: 1. Create a project in Vivado 2017.2, a project consist of a Zynq and just one custom IP core, a led controller just to turn on and of the 4 leds on board. 2. I have successfully generated the bitstream and exported the hdf in SDK. 3. In SDK I have created a project for build the fsbl successfully 4. I have built u-boot ( git clone from xilinx repo on github ) just changing the zynq_common.h file to load just the kernel and the devicetree ( not the uramdisk because I would like to put the rootfs on sd card 2nd partition ) 5. I have built the kernel ( always from xilinx github ) using the zybo_zynq_defconfig as configuration and I have successfully generated the uImage 6. I have prepared a ubuntucorearmhf rootfs 7. I have packaged into BOOT.BIN file the fsbl, bitstream and u-boot 8. I have used the devicetree generator from xilinx github to generate my devicetree ( files attached ), with modified bootargs properly ( I hope ) 9. As you can see there is no PHY into pcw.dtsi or zynq-7000.dtsi so I have added that into a file called ethernet.dts ( made by me ) including the system-top.dts just to leave the auto-generated devicetree without modification. 10. I put the BOOT.BIN , uImage and devicetree.dtb ( compilation of ethernet.dts ) into the 1st partition of my sdcard, the rootfs into 2nd 11. At boot time the system boots without problem but it says that there is no PHY for ethernet and if I do an ifconfig the eth0 interface is absent. I have done a mistake on binding the PHY for realtek ethernet controller?? Another step I have tried is to use the BOOT.BIN and the image.ub provided by Digilent on zybo bsp 2015.4 (Digilent-Zybo-Linux-BD-v2015.4) and like this the PHY has been found and I can see the eth0 interface. I have also tried to understand the difference between my devicetree and the Petalinux one ( see .txt file ) without success. I have tried to use your zybo_base_system project instead of a clean project from scratch with same results. I have finally tried this https://github.com/MarioLizanaC/Linaro-O.S.-for-Zybo/ , a project found on github where a guy boot Linaro ( I have done it with Ubuntu core ) using as start I think your zybo_base_system but with 3.18 kernel instead of 4.9 kernel and Vivado 2015.4 instead of Vivado 2017.2 . Thanks in advance. Michele ethernet.dts pcw.dtsi system-top.dts zynq-7000.dtsi gem0_node_petalinux_bsp.txt
  20. Monics

    Ethernet shield

    I am looking at using the Digilent modules together with Labview LINX (Makerhub), and I need a setup with ethernet connection to Labview/LINX. Digilent have retired the 410-211, Network Shield... but will I be able to use the Pmod NIC100 (together with max32 or uC32) and get support for ethernet interface through LINX....?Br,Martin Christiansen.
  21. Hi, I am looking to implement the use of Ethernet port of the Zybo board without Zynq PS. I am using Windows OS and Vivado 2017.2. I have already implemented the Iwip echo server project. Is there any suggestions or guideline about the use of Ethernet port on Zybo without Zynq PS? Thank you in advance. BR ALI
  22. Hi, I have the Zynq 7000 board (Z-7010). I'm trying to build a Vhdl Program that sends and basic Ethernet Frame throw the RJ45 onboard interface. I'm trying the Intr_Dma example to learn how to use the controllers on the PS. My block design is simply one block of Zynq7 Processing system with eth0 and UART1 enabled Exported the hardware to SDK and imported the example of emacps "xemacps_example_intr_dma.c". Run the program will show the following message from UART: "Entering into main() Error setup phy loopback" Debugging the program and I found the problem is inside function EmacPsUtilEnterLoopback of xemacps_example_util.c This function is to set the PHY chip to loopback mode. However, This functions only works for Marvell and TI chip. according to this great blog, this should work: http://igorfreire.com.br/blog/#zynq-ethernet-interface-zybo-board i'v tried troubleshooting this problem,i'v added the fallowing lines:(to the "EmacPsUtilEnterLoopback" function) printf("%d\n",PhyIdentity); printf("%d\n",PHY_ID_MARVELL); printf("%d\n",PHY_ID_TI); the output is: Entering into main() 28 321 8192 Error setup phy loopback Therefor the realtec phy has PhyIdentity of 28, marvell phy is 321 and Ti phy is 8192. i'v tried changing the following lines: if (PhyIdentity == 28) { printf("phy is Marvell\n"); Status = EmacPsUtilMarvellPhyLoopback(EmacPsInstancePtr, Speed, PhyAddr); } after it didnt work, i've tried this lines: if (PhyIdentity == 28) { printf("phy is TI\n"); Status = EmacPsUtilTiPhyLoopback(EmacPsInstancePtr, Speed, PhyAddr); Nothing works. where can i find the relevant code? Thanks, David
  23. Hello, I have the Zynq 7000 board (Z-7010). I'm trying to build a Vhdl Program that sends and basic Ethernet Frame throw the RJ45 onboard interface. so far i'v constructed the Frame itself according to the Ethernet IEEE 802.3 standard, now i see there are Gmii and Rgmii Interface and a builtin Phy controller but i cant understand how to use them all. Is there a simple example of such a program? - I use the 2017.1 Vivado and the Z-7010 Board. Thanks.
  24. I have a ZYBO Board working fine with linux3.18. I have tested UART, I2C and Ethernet using linux3.18. But I needed to update my linux to 4.9, now ethernet cannot be configured. when I give ifcofig -a lo Link encap:Local Loopback LOOPBACK MTU:65536 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1 RX bytes:0 (0.0 B ) TX bytes:0 (0.0 B ) sit0 Link encap:IPv6-in-IPv4 NOARP MTU:1480 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1 RX bytes:0 (0.0 B ) TX bytes:0 (0.0 B ) It lists lo and sit0 and no eth0. I have searched web for a solution, but could not get anything useful. an someone help?
  25. Turn your Nexys Video board into something useful for hardware development by adding the IO capabilities of another FPGA board. In this project the other board is a Digilent Spartan 3A Starter board. But it has a lot of resources that make it useful for a variety of projects needing an FPGA. The "magic" is supplied by those wonderful Ethernet PHY modems. Release 3 offers two target boards, Gigabit and 100 Mbps designs. Check it out even if all you want to do is connect any two FPGA boards with Ethernet capability. IO_EXPANDER_R3.zip