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Found 105 results

  1. har

    Issue with Spartan 3E kit

    Hi, I had recently ordered a spartan 3E kit from digilent . However, it seems the kit is not functioning properly I loaded a simple program onto the kit but there was no expected behaviour everytime four fixed LEDs lit up, irrespective of me changing the code. Could you please help or divert me to the appropriate contact I have already sent an email regarding this to the sales team and wish this issue gets addressed as early as possible. Thanks
  2. sudhir

    Basys 2 Board not working

    Just bought a brand new Basys 2 from an authorized dealer in India. I connect the Basys 2 and load Adept and get an " "Initialization Failed. Check connections and try again". After which I get "Found device ID: ffffffff Initialization Failed." in the Adept Screen! Any idea what to do? I'v bought many boards from Digilent and this is the first time I'v seen this error. Someone PLEASE HELP! PS: It's not been even a month since I bought this board. Do we have any warranty?
  3. jmh

    Basys3 crashing windows 7

    Often windows7 crashes with the blue screen when I turn off the power switch of the Basys3. Any ideas or suggestions? Thanks, John
  4. Hi all, I have a Zybo Zynq-7000 Development board, and I'm attempting to create a design that uses the bidirectional HDMI port as an input. I want to take the HDMI input (with a desktop or laptop as the source) and write the video stream to memory, and then access the data in a Linux environment (I am using Xilinux, a graphical, Ubuntu 12.04 LTS-based Linux distribution for the Zynq-7000) to eventually send out the data over the internet. I'm having a bit of difficulty understanding how to correctly implement the design in Vivado (2014.4) which is why I'm here. I'm trying to use as many standard Xilinx or Digilent IP cores as possible to make the design straightforward since I am new to FPGA and Vivado. After wading through tons of documentation, I feel like I have a decent understanding of the general design flow for a video design, but as I said I do not have much experience here so I am looking for someone to hopefully point out my mistakes or point me in the right direction. My current design uses a DVI2RGB IP core provided by Digilent (found here: which is then interfaced with the Xilinx Video In To AXI4-Stream IP Core (documentation found here:, which then goes to the Xilinx AXI Video Direct Memory Access (VDMA) IP core (documentation found here: Finally, the output of the VDMA is interfaced with an AXI Memory Interconnect to connect it all to the processing system. I do not want to output the video stream that is being written to memory to a display output such as VGA, simply access the video data in Linux and send it out over the internet. A few questions: 1. First and foremost, does my thought process for the design outlined above make any sense? 2. Do I need to use the Video Timing Controller and subsequently the Video Timing Controller IP cores for a design such as this? My assumption here is NO since the input is providing the clock (which in Vivado is being provided to the Video In To AXI4 and VDMA cores), and nothing is being outputted. 3. The DVI2RGB IP Core takes in TMDS as its input. Do I simply create ports labeled TMDS_Clk_p etc and connect to the input of the IP core? How does Vivado know (and subsequently, how does the board know) those ports I created are supposed to be for the HDMI input port? 4. Assuming my design works and I can successfully write the inputted video stream into memory using the VDMA, is the Xilinx Linux VDMA Driver (found here: my best bet for accessing the data in the VDMA in Linux? Or is Video4Linux2 (V4L2) something that I should be using here? I've read that V4L2 has compatibility with VLC which seems like a convenient way to then stream the video data over the internet. Additionally, I was able to import an EDK HDMI_RX IP core into Vivado that is used in a Digilent GoPro Video Filtering Project (found here: I be attempting to use this core instead of the DVI2RGB core? I chose the DVI2RGB because it was designed for Vivado rather than EDK, so I assumed it would be easier to use. I would eventually like my design to incorporate audio as well though, which I know DVI doesn't do. Comments, criticism, advice, help; whatever you've got, it is very welcome here! Anything to steer me in the right direction. Sorry for the long post guys, I've always been a bit verbose I'll attach a screenshot of my Vivado block design to hopefully illustrate some of the things I mentioned about my design. Thank you, Chris
  5. I'm using atlys LX45 and I wrote to C programs.I want to transfer data from one side to another but when I debug one of the 2 programs using getfsl I didn't receive any informations.So how can I fix this problem??
  6. fabio

    HDMI output on Zedboard

    Hi guys, is my first time here and i have a problem with the zedboard. I have to enable the HDMI output on the board, but i didnt find the right tutorial for vivado 2014.4. I have my own bitstream and i have to integrate it with another one that implements HDMI. I hope you can help me, thank you so much.
  7. ks0ze

    JTAG SMT2 chain limit

    Is there a limit on the number of devices the JTAG-SMT2 module can reliably have in the chain? Thanks, Dan
  8. On the chipKIT Uno32, uC32, DP32 and WF32, the interrupt is raised for every byte in I²C slave mode. The corresponding MCUs are the PIC32MX320F128, PIC32MX340F512H, PIC32MX250F128B and PIC32MX695F512L. I don't know for other boards / MCUs as I've only tested with those I own. This bug/feature was confirmed at chipKIT forum and there's a related issue at the GitHub repository I2C wire library & repeated start (Sr) onReceive(handler) issue Slave Receive Problems I2C Wire Library Limited to 1 Byte in Slave Mode Unfortunately, the question hasn't received any official answer yet. The suggested work-around isn't reliable as it requires to be set for every I²C master. Is it a bug?
  9. Hi! I am currently working on a project which uses a particular version of an ARM Cortex M0. Therefore I can not use Xilinx' tools to debug the ARM core directely. Using a Nexys 3 with a Spartan 6 I am looking for other ways to debug it: In the ARM forum a user pointed out that ARM has a debugger platform called CMSIS-DAP. Does Digilent support this platform? I currently use a JTAG USB debugger from Digilent, does it support CMSIS-DAP?If not, do you know of any other possibility on how I could debug the ARM core directly and without using Xilinx tools?Any help is much appreciated!
  10. ingmar

    Nexys4-ddr Board Files

    I've just downloaded the "latest?" board files for the NEXSYS4 DDR and they appear to be buggy and preventing the MIG from generating.. Vivado 2014.3.1 complains with: Any suggestions? Cheers, Ingmar, Canberra, Australia
  11. Hello, I am fairly new to linux and I am trying to program a cerebot nano. I have the JTAG-USB cable with SPI, rev. b. I have downloaded wine and the AVR programmer but I don't see the device when I enumerate in the AVR programmer. If I use djtgcfg enum, from the terminal: chris@chris-T510 ~ $ djtgcfg enum Found 2 device(s) Device: DCabUsb Product Name: DCabUsb1 V2.0 User Name: DCabUsb Serial Number: 50003C003874 I did install the usb drivers that came with the AVR programmer, using wine. Any ideas?
  12. Hi, I'm hoping to PWM an extra bit(s) out of the LSB of the VGA DAC on the Neyx4ddr board so I'd like to know what kind of bandwidth the VGA DAC has. On the schematic it has a 4k resistor, but what's the capacitance ?
  13. zygot

    Genesys DDR with ISE 14.7

    I need to use the Genesys DDR2 SODIMM connected to logic ( no soft processor ) using the ISE flow instead of XPS. Has anyone at Digilent a working project similar to the DDR test available for the Atlys board? Curiously, the MIG tool doe not let me assign the correct pin to the ddr_wen signal.
  14. I originally posted an issue we're having connecting a CPLD programming cable to parallel connectors, but I haven't heard anything in a while, so I am making a new thread. here is my original question: "Hi, I have a CPLD prgramming cable and connecting it to a Xilinix pn XC9572XL-5VQG44C. The issue I'm having is getting it to connect to our parallel ports. We've been troubleshooting this for some time, and haven't been able to get anywhere. From what I can tell, there is nothing wrong with our parallel ports (3 of them are brand new, and 1 of them has been used for a while.). I would really appreciate it if someone could give me a call to make sure we have everything setup properly. You can reach me at 314-300-6147." This is the response I got: "Hello, What kind of programming cable are you using ? Please be sure to use "real" parallel ports, as the parallel converters (like USB to parallel) won't work with programming cables. Regards, Cristian" To answer your question, I have a JTAG programming cable. Some are connected to USB to Parallel ports. I understand that those will not work. However I have 3 others that are connected to parallel cards, or onboard parallel, but only 1 port works with it. I would really appreciate it if someone could give me some help regarding this. 314-300-6147. Thanks.
  15. Hi, I have a CPLD prgramming cable and connecting it to a Xilinix pn XC9572XL-5VQG44C. The issue I'm having is getting it to connect to our parallel ports. We've been troubleshooting this for some time, and haven't been able to get anywhere. From what I can tell, there is nothing wrong with our parallel ports (3 of them are brand new, and 1 of them has been used for a while.). I would really appreciate it if someone could give me a call to make sure we have everything setup properly. You can reach me at 314-300-6147. Thanks!
  16. hi i am trying to cummunicate to pc with fpga board. i am using atlys board of digilent company in which spartan-6 (xc6slx45csg324c) is connected to marevell 88E1111 phy chip. my frame is:- constant udp_frameA :frame60:= (x"FF",x"FF",x"FF",x"FF", -- mac dest x"FF",x"FF",x"00",x"00", x"00",x"04",x"14",x"13", -- mac src x"08",x"00",x"45",x"00", -- IP header x"00",x"2E",x"00",x"00", x"00",x"00",x"40",x"11", x"7A",x"C0",x"00",x"00", -- IP src x"00",x"00",x"FF",x"FF", -- IP dest x"FF",x"FF",x"00",x"00", -- port src x"50",x"DA",x"00",x"12", -- port dest + len x"00",x"00",x"41",x"41", -- checksum udp + data "A" x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41"); and i am getting same frame on simulation and chipScope but i am not getting this frame in proper order on Wireshark. Wireshark result attached with it. please find this attachment. please respond me as soon as possible.
  17. Hello everyone, I am interested in purchasing a simple developing board to develop (more or less) an RFID emulator. Basically the chip only has to drive an RF SPDT connected to one of its pins based on some logic that I will implement. Initially I will just just need to have some data (2-3 kB) saved in memory that I will encode using Hamming(16,10) and send it to the SPDT with a rate of 5Mbits/sec. I am fairly new to FPGA developmen and although I have written some VHDL (a simulation of the tomasulo algorithm, a simple ALU during my undergrad), I consider myself a complete newbie. Do you guys have a recommendation for an FPGA dev kit with a simple programming interface(e.g. USB), preferably compatible with linux AND windows machines? I suspect that the logic that I am going to download will not occupy too much space so I don't need a large in terms of LUT's FPGa but I might need to do some signal processing so I would prefer something with the "newest technology" (talking newbish here). Moreover, I am very concerned about the toolchain, I have used webkit in the past and, well I will just say that I don't expect much from the newer versions. Is there anything better or do you have any suggestions. I am not really concerned about paying for a 1000$ license if I can save a month of bug/driver/compatibility nonsense. I also want to buy PC and I am looking for something that will be able to handle all the driver/connectivity/performance constrains that are associated with the toolchain. I have payed for a 1000$ Dell once with a fake PCIe4 port and I don't want to have the same experience again. see here Thank you very much in advance Lefteris
  18. I am trying to get the PMOD PMON1 to run on a teensy for a micro project I am working on and so far not so good. Here is my code block, please take a look and let me know if you see anything I am missing? I far I am not Serial reading anything but the "Program Started". /* ADM1191 U/I I2C converter I2C SDA ==> 18 I2C SCL ==> 19 CONF_REG[7..0] NC STATUS_RD NC VRANGE I_ONCE I_CONT V_ONCE V_VCONT V_VCONT =1, countinuosly cnv V I_VCONT =1, countinuosly cnv I VRANGE Vrange =0 -> Vr=26.52V, write I2C [ADR][CONF_REG] read I2C [ADR][Uh][Ih][Ul:Ih] */ #include <Wire.h> #define ADM1191_ADR B01100000 // 7bit ADM1191 device address A1,A0=00 jumpers set to 1 0Xb00 #define ADM1191_CONF_REG B00000101 // ADM config uint16_t result_Uh=0, result_Ih =0, result_UIl =0; float P, Uh, Ih, Rs=0.05; void setup() { while(!Serial); Serial.print("Program Started"); Serial.println(); Serial.begin(9600); Wire.begin(); Wire.beginTransmission(ADM1191_ADR); Wire.write(ADM1191_CONF_REG); Wire.endTransmission(); } void loop() { Wire.beginTransmission(ADM1191_ADR); Wire.requestFrom(ADM1191_ADR, 3); // request 3 bytes from ADM while(Wire.available()) { result_Uh =; // HIGH U result_Ih =; // HIGH I result_UIl =; // LOW U : LOW I result_Uh = (result_Uh << 4) + (result_UIl >> 4); result_Ih= (result_Ih << 4) + (result_UIl & 0x0F); Uh= (26.52/4096)* result_Uh; Serial.print(" U: "); Serial.print(Uh, 2); Serial.print(" [V]\t"); Ih= ((105.84/4096)*result_Ih)/Rs; Serial.print(" I: "); Serial.print(Ih, 0); Serial.print(" [mA]\t"); P= Uh*Ih/1000; Serial.print("P: "); Serial.print(P, 2); Serial.println(" [W]\t"); } Wire.endTransmission(); delay(1000); }
  19. laplacier

    xst.exe not found

    Hello there, I'm a beginner to FPGA boards. I only learned about them recently and I purchased a Nexys3 along with a Digital Design Using Digilent FPGA Boards (2012) textbook available from this website in order to get familiar with them. I've been following the textbook religiously but I've come into an issue when I attempt to use the Synthesis Tool on Active-HDL Student Edition. I put in the settings to get it running as instructed by the textbook and I get the following error: I've attached as much information in pictures as I can. I have located xst.exe and pointed to its location for the Synthesis Tool but the program seemingly does not acknowledge it. Any ideas?
  20. Hi All, I am newbie to zynq board, eagerly started to learn. I have digilent HDMI FMC card it supports 8,10,12 bits color depth. I am trying with pixel width 10-bits with xilinx zynq zc702 board. previously we used Avnet HDMI FMC card it supports only 8-bit pixel width.Now we are in need to move with 10 and 12-bits pixel width. 1. What are the things needed to use digilent fmc card with zync zc702 board. 2.Where i can get drivers (c-code libs) for digilent fmc card. 3.While its operating in 10-bit mode should i connect it with 10-bit color depth output of laptop? 4.Can i use Avnet fmc card drivers for this digilent fmc card too ? (in this case i need to change EDID content w.r.t digilent fmc card) 5. Kindly help me regarding this, It would be a great help to me..!!! I Tried as Mentioned Below : 1.I am not having the digilent fmc card drivers to use and compile it with my application C-code so i used with some changes of Avnet fmc card driver C-codes. Also chnaged the EDID content w.r.t digilent fmc card ref Document. 2.I used lenova G580 lap to connect HDMI o/p from laptop to FMC card using HDMI cable.digilent fmc card mode is pixel width is 10-bit but while looking at Graphics card properties of Lap shows that the color depth is 32-bit output, I am sure whther it will support the 10-bit mode digilent fmc card. 3.Any how, While running it I am facing the error message which is given below, Error: ADV7611 has NOT locked on incoming video, aborting ! Thanks, Ramesh
  21. hii am trying to cummunicate to pc with fpga board. i am using atlys board of digilent company in which spartan-6 (xc6slx45csg324c) is connected to marevell 88E1111 phy chip.In this project i am facing the problem to getting the mac address of board (phy chip) to send the arp frame and udp frame.because i am manually framming the udp and arp frame fr in my code for which i need source mac address i.e mac address of fpga board (or marvell phy chip).please respond me as soon as possible. constant udp_frameA :frame60:=(x"FF",x"FF",x"FF",x"FF", -- mac destx"FF",x"FF",x"00",x"00", x"00",x"04",x"14",x"13", -- i want to know this source mac address.x"08",x"00",x"45",x"00", -- IP headerx"00",x"2E",x"00",x"00",x"00",x"00",x"40",x"11",x"7A",x"C0",x"00",x"00", -- IP srcx"00",x"00",x"FF",x"FF", -- IP destx"FF",x"FF",x"00",x"00", -- port srcx"50",x"DA",x"00",x"12", -- port dest + len x"00",x"00",x"41",x"41", -- checksum udp + data "A"x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41",x"41");
  22. Hi. I managged to run both Linaro and ArchLinux on the Zybo board, with HDMI output (but i'm gonna remove it after). But I'm having some troubles to comunicate with my custom hardware. I'm used to programming in Hardware, and I made several real time high performance applications like face recognition and real time video processing on pure verilog (Nexys 3, Nexys 4, Atlys boards), but I'm kind of new to cross-compiling, linux kernels, and drivers. I have a few master AXI modules that directly communicates with the DDR3 memory using the HP ports (no DMA, VDMA or similiars), and I just reserve a fraction of the DDR3 memory to work with them. Now in Linux, all the address are virtual, so I must write a driver, or find a way to allocate physicall contiguous memory in software. -My IP usually work this way (e.g this is a sobel filter): It receives the base address where the image to process is located (usually is XRGB888 format), the resolution of the image, several arguments like threshold, and it outputs directly the result on the VGA port or HDMI port or a touchscreen that I have (all of them are custom IP) or it write the output on the DDR3 memory. If the flow requires SW interventions, It triggers a interrupt. Now that I'm using Linux, I have 3 options: Use DMA: I kind of know how to use DMA on baremetal on the software side, but I have no idea how to make a custom IP that comunicates with the DMA modules. I have a decent understanding how master and slave AXI full interfaces works tough.Write a custom driver that works the way my IP needs.Hack with things like dma-mapping, contiguous memory allocations, memory maps, etc.Make a "don't touch" region of ram for Linux, so the HW can work with it.With simple AXI peripherals that are mapped to a fixed address (0x4XXXXXXX) and doesnt communicate with the DDR3, I use mmap and to access the registers, and it work well, but I can't use interrupts. With peripherals that use the DDR3, the configuration parts is done the same way that the regular AXI peripherals, but the RAM buffer, needs to be reserved so Linux doesn't write to it, or it only do it on my command. Also I need the physicall address of that reserverd ram region to pass it to the peripheral. I'd like some highlights on how to make a custom DMA module (hardware side please), but any of the 4 options works. PS: Also, some of these modules that work with RAM doesn't even have an slave axi interface, so they won't appear on the automatic generated device tree. Any information would be usefull. Best regards. Alejandro Wolf.
  23. Hello experts, I'd like to use the all signals of the pmods (excepted MIO pmod) as single ended lines. I have read the post: however there are no description how to set the ports as a single ended lines. I have tried to make it straight forward in the ucf file as following: NET "line1" LOC=W19 | IOSTANDARD=LVCMOS33; #IO_L22N_T3_34 NET "line2" LOC=W18 | IOSTANDARD=LVCMOS33; #IO_L22P_T3_34 Unfortunately all signals with "N" (e.g. IO_L22N_T3_34) are set to -3.3V (MINUS 3.3V measured to ground) if I set the output "HIGH". How can I use this differential pair as single ended with +3.3V (PLUS 3.3V) as HIGH output and (ZERO) 0V as "LOW". (Measured to ground) Thanks in Advance
  24. Hi all, I have a problem with my CoolRunner-II CPLD Starter Kit (Revision 2.0). I know this is an outdated product which is not supported by the latest version of Adept. But I had a look at the schematics of the current revision 3.0 and I noticed that the USB to JTAG controller is the same MCU like the one in revision 2.0. I'd like to know if it would be possible to reprogram the firmware of that controller and get my board to work with the latest Adept version. Or is there another solution to use the board with a Xilinx iMPACT plugin? (I use ISE 14.7 on Windows 7 64 Bit) I already tried to use the latest plugin but I can not connect. As soon as I connect my Nexys 2 Board the plugin works fine. I would be very happy if there was a way to work with my CoolRunner II without having to buy any additional JTAG cable or another Coolrunner-II Starter Kit which is almost the same like the one I already own. Do you have any suggestions for me? Best regards,jago
  25. Hi, some news about Nexys4-DDR Resource Center updates? ​I bought the board and I'm interested in sections: - Embedded Linux Materials - Advanced Microblaze Design with MIG, Ethernet, UART & GPIO - Constraint Files - Xilinx Memory Interface Generator (MIG) Project - XADC Demo