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Found 105 results

  1. Hello I have a problem with AES-XLX-V5LX-EVL110-G when I implement of following examples V5LX Evaluation Boot Loader Example Design V5LX Evaluation Interrupt Example Design V5LX Evaluation Xilinx Micro Kernel (XMK) Example Design V5LX Evaluation lwIP Web Server Example Design V5LX Evaluation System ACE Module Example Design in part of programming fpga for Jtag, i have folloguin error: Creating backup of last automatically saved project to 'C:\Xilinx\14.3\ISE_DS\ISE\auto_project_1.ipf'. Enumerating cables. Please wait. Connecting to cable (Usb Port - USB21). Checking cable driver. Driver file xusb_emb.sys found. Driver version: src=1029, dest=1029. Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS 14:14:44, version = 1021. ======================================================= Found cable - > ESN device is not available for this cable. No ESN. ======================================================= Connecting to cable (Usb Port - USB22). Checking cable driver. Driver file xusb_emb.sys found. Driver version: src=1029, dest=1029. Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS 14:14:44, version = 1021. ERROR:iMPACT - Cable not found, ESN: 00000000000000 INFO:iMPACT - Failed to open file: -- File ? --, replace with 'bypass'. INFO:iMPACT:501 - '1': Added Device unknown successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- INFO:iMPACT - Failed to open file: -- File ? --, replace with 'bypass'. INFO:iMPACT:501 - '2': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- INFO:iMPACT - Failed to open file: -- File ? --, replace with 'bypass'. INFO:iMPACT:501 - '3': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- Active mode is BS Loading collection Untitled. Design rev0 Version 0. Design rev1 Version 1. Project: 'C:\Xilinx\14.3\ISE_DS\ISE\auto_project.ipf' loaded. GUI --- Auto connect to cable... INFO:iMPACT - Digilent Plugin: Plugin Version: 2.4.3 INFO:iMPACT - Digilent Plugin: no JTAG device was found. AutoDetecting cable. Please wait. *** WARNING ***: When port is set to auto detect mode, cable speed is set to default 6 MHz regardless of explicit arguments supplied for setting the baud rates PROGRESS_START - Starting Operation. Connecting to cable (Usb Port - USB21). Checking cable driver. Driver file xusb_emb.sys found. Driver version: src=1029, dest=1029. Driver windrvr6.sys version = 10.2.1.0. WinDriver v10.21 Jungo (c) 1997 - 2010 Build Date: Aug 31 2010 x86_64 64bit SYS 14:14:44, version = 1021. Cable PID = 0008. Max current requested during enumeration is 74 mA. Type = 0x0004. Cable Type = 3, Revision = 0. Setting cable speed to 6 MHz. Cable connection established. Firmware version = 1303. File version of C:/Xilinx/14.3/ISE_DS/ISE/data/xusb_xlp.hex = 1303. Firmware hex file version = 1303. PLD file version = 0012h. PLD version = 0012h. PROGRESS_END - End Operation. Elapsed time = 1 sec. Type = 0x0004. ESN device is not available for this cable. Attempting to identify devices in the boundary-scan chain configuration... INFO:iMPACT - Current time: 22/09/2015 10:34:18 PROGRESS_START - Starting Operation. ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- Identifying chain contents...INFO:iMPACT:1588 - '0':The part does not appear to be Xilinx Part. '0': : Manufacturer's ID =Unknown , Version : 10 INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- '1': : Manufacturer's ID = Unknown INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- INFO:iMPACT:1588 - '2':The part does not appear to be Xilinx Part. '2': : Manufacturer's ID =Unknown , Version : 15 INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- done. PROGRESS_END - End Operation. Elapsed time = 0 sec. I use this programmer https://www.digilentinc.com/Products/Detail.cfm?NavPath=2,395,716&Prod=XUP-USB-JTAG can you help me? thanks Leo
  2. Evocati

    Zybo HDMI sink

    Hi everybody, I am working on a Zybo project similar to what has been done here. What I wanna do is simple: go pro -> HDMI -> Zybo -> VGA -> monitor So I use dvi2rgb and rgb2vga IPs just like what Marshall did in the above post Marshall's schematic: https://forum.digilentinc.com/uploads/monthly_2015_05/zybo_passthrough.png.efb9f569b3fabcb8a452c95dc1ccc1e2.png So I followed the above design. But there is just no image coming on the monitor. So then I decided to only connect the dvi2rgb module and test if there is any signal coming out: go pro -> HDMI -> Zybo -> pixelClk to on-board LED Output the pixcelClk and connected it with the on-board LED and a counter(couting 75M so the flashing LED can be recognized by my eyes.) My schematic: http://s19.postimg.org/ju2odjvup/hdmi_3_schematic.png Still the LED doesn't flash. I am not sure if there is something wrong with the way I configure the DDC part for dvi2rgb or if the code of dvi2rgb needs to be modified before using(Jieming mentioned in the above post). Has anyone met similar problems? Thank you for your time and any help or suggestions are really appreciated. Hao
  3. cbg

    Nexys 4 PMOD spacing

    Hello, I'm designing an adapter PCB to interface with the three PMOD connectors on the right hand side of the Nexys 4 (JADC, JC, JD). I can only find a schematic but in order to have the correct spacing between the connectors I would need a board file or a CAD file or the like. The reference manual doesn't have any measurements either. Has anybody got the measurements or a file where I could read them? Thanks in advance!
  4. Hello I'm using BASYS2 at Digilent Co. and Studying Ambient Light Sensor Pmod. I think below source code is correct, but not working on my board. clk : 50Mhz sclk : 1Mhz cs : sclk x 16 count data 8bit ( dout is 1bit data) LED : output and check of information by Ambient Light Sensor My source code is below. but it's not working on BASYS2 board. (I did and saw test bench simulator, but there is correct output pulse LED etc) I don't know what is error . So Please some imformation or advice LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY SPI3 IS PORT( clk : IN std_logic; clr : IN std_logic; dout : IN std_logic; led : OUT std_logic_vector( 7 DOWNTO 0 ); sclk : OUT std_logic; cs : OUT std_logic ); END SPI3; ARCHITECTURE SPI3_be OF SPI3 IS TYPE state_type IS( idle, adc_r, adc_w ); SIGNAL state : state_type := idle; SIGNAL cnt_sclk : INTEGER RANGE 0 TO 49; SIGNAL newsclk : std_logic := '0'; SIGNAL cnt_cs : INTEGER RANGE 0 TO 1599; SIGNAL newcs : std_logic := '1'; SIGNAL data : std_logic_vector( 7 DOWNTO 0 ); SIGNAL cnt_data : INTEGER RANGE 1 TO 16; BEGIN sclk <= newsclk; cs <= newcs; clkdiv : PROCESS( clr, clk ) BEGIN IF clr = '0' THEN cnt_sclk <= 0; cnt_cs <= 0; newsclk <= '0'; newcs <= '1'; ELSIF clk'EVENT AND clk = '1' THEN IF cnt_sclk = 49 THEN newsclk <= NOT newsclk; cnt_sclk <= 0; ELSE cnt_sclk <= cnt_sclk + 1; END IF; IF cnt_cs = 1599 THEN newcs <= NOT newcs; cnt_cs <= 0; ELSE cnt_cs <= cnt_cs + 1; END IF; END IF; END PROCESS clkdiv; FSM : PROCESS( clk, clr, state ) BEGIN IF clr ='0' THEN cnt_data <= 1; data <= "11111111"; ELSIF clk'EVENT AND clk = '1' THEN CASE state IS WHEN idle => IF newcs = '1' THEN state <= idle; ELSIF newcs ='0' THEN state <= adc_r; END IF; WHEN adc_r => IF cnt_data >0 AND cnt_data <4 THEN cnt_data <= cnt_data + 1; state <= adc_r; ELSIF cnt_data > 3 AND cnt_data <12 THEN cnt_data <= cnt_data + 1; data( 11 - cnt_data ) <= dout; state <= adc_r; ELSIF cnt_data > 11 AND cnt_data <16 THEN cnt_data <= cnt_data + 1; state <= adc_r; ELSIF cnt_data = 16 THEN state <= adc_w; END IF; WHEN adc_w => led <= data; cnt_data <= 1; state <= idle; END CASE; END IF; END PROCESS FSM; END SPI3_BE;
  5. Was wondering if the FPGA I/Os on this connector have controlled impedance and matched trace lengths. If matched, is it just to the complementary signal or are all signals the same trace length. The signals will be used as single-ended instead of differential. I have a high speed digital application that has CLK-to-signal and signal-to-signal timing constraints. Please help. Thank you.
  6. I wanted to see what video standards my Nexys Video design would work with, so I took the board into work and connected it up to a Sencore Mediapro Multimedia Generator (e.g. https://www.testequipmentconnection.com/47221/Sencore_MP500.php). Strangely *nothing* worked 720p, 1080i 1080p, 50Hz, 60Hz - not even when it was generating DVI-D. Equally strange, even the HDMI/DVI-D pass-though in the design in board's flash didn't work. However, the monitor worked just fine when it was plugged directly into the Sencore. Connecting up the logic analyser to debug signals showed unpredictable runt pulses on the HSYNC line, and after tracing and analysing an entire frame there are blocks of CTL symbols where they shouldn't be. Plugging the Nexys Video back into my Laptop or Media player everything is fine. Not sure what is up, but something is. I tried a couple of different HDMI cables without success. It looks to be something at the physical layer... can anybody offer any advice? Test idea #1 - I'll put a HDMI splitter between the Sencor and the board. Test idea #2 - I'll manually decode the 50MB of captured symbols (well, write a program to do it) and see if that shows anything...
  7. Hi, i´m using the UNO32 with Mpide. I connected the UNO32 with a external sd card and the MRF24WG0MA wifi modul from Microchip. Together they work exactly like the Wifi shield (e.g. the CKEasyWifiConfig ConfigFromSD example works/worked). But now my Pin 10 is broken and i want to use a other chip select pin for the Wifi module. Can someone please tell me where i can change the chip select pin for the wifi shield?In addition i use another SPI device and also I2C. I have problems using the SPI/DSPI librarys together with the SD library. Are the following librarys compatible with DSPI.h and Wire.h?#include <WiFiShieldOrPmodWiFi_G.h> #include <DNETcK.h> #include <DWIFIcK.h> Thank you and sorry for my english.
  8. Good evening, We are members of a research team from N.K. University of Athens and ICCS and we are considering NetFPGA-SUME for a research project. The NetFPGA-SUME is equipped with a SAMTEC QTH-DP connector (connected to 8 high-speed serial links). We would like to ask you, if there is a SAMTEC product that directly fits to this connector and has 10Gbits+ SMA pair output ports or another product that we can use with the QTH-DP SAMTEC connector to expand to an FMC with SMA ports (preferably first option). We would like to discuss the available options (I/Os etc) and the pricing of each product, Best regards, Ioannis Patronas
  9. Hello, I just got a WF32 chipKit board. I want to start out with performing a simple tcp client HTTP get request. Something like have the board do a request for "http://192.168.1.5/test" just to see the request show up in my server logs. All of the examples I have found are using the WF32 as a web server, not as a client. Does anyone have code or a link to code that shows how to do a simple client http request like this? Thanks!
  10. hello, my CPLD Starter Board rev2 is not working on Win7, i like to update the Atmel Firmware AT90USB162 on my CoolRunner-II CPLD Starter Board rev2 (PN SK-CRII-L-G), -> can you send me the Atmel Firmware AT90USB162 used on CoolRunner-II CPLD Starter Board rev3 (PN 410-146P-KIT) ? (i checked, AVRISP mkII programmer is compatible with AT90USB162) thank you, best regards
  11. hi, I am using PMOD AD1 and PMOD DA2 on ZC702 Eval Board but it dose not work. Befor that I used my code with spart 3a, spartan6 and zedboard and my code work for all of them but when I used that code for the zc702 it dose not work. I use clock division to send 20 Mhz : This is my code: library ieee; use ieee.std_logic_1164.ALL; --use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.ALL; use ieee.numeric_std.all; Library UNISIM; use UNISIM.vcomponents.all; entity ad1_da2 is port( SCLK_P : in std_logic; SCLK_n : in std_logic; CS : out std_logic; -- chip select for ADC(active low) SYNC : out std_logic; -- SYNC for DAC DIN : in std_logic; -- ADC DOUT : out std_logic; -- DAC SCLK : out std_logic; -- ADC SCLK2: out std_logic -- DAC ); end ad1_da2; architecture Behavioral of ad1_da2 is component IBUFGDS is port ( I : in std_logic; IB : in std_logic; O : out std_logic ); end component; -- FSM states type state_type is (IDLE, READ_DATA, FUNC, WRITE_DATA); -- initial state signal state : state_type := READ_DATA; -- data from the ADC signal data : std_logic_vector(11 downto 0); -- counter variable signal cnt : integer range 0 to 20 := 0; -- counter for clock division signal clkdiv : integer range 0 to 10; -- new clock from division signal newclk : std_logic := '0'; signal risingedge : std_logic := '1'; -- reset signal signal reset : std_logic := '0'; signal clk : std_logic; begin SCLK <= newclk; SCLK2 <= newclk; begin if (reset = '1') then elsif (rising_edge(CLK)) then if (clkdiv = 10) then -- divide 200MHz by 10 risingedge <= risingedge xor '1'; newclk <= newclk xor '1'; clkdiv <= 0; else clkdiv <= clkdiv + 1; end if; end if; end process clock_divide; main : process (CLK, reset) begin if (reset = '1') then elsif (rising_edge(CLK)) then if (clkdiv = 10 and risingedge = '1') then case state is when IDLE => CS <= '1'; SYNC <= '1'; if (cnt = 16) then cnt <= 0; state <= READ_DATA; else cnt <= cnt + 1; state <= IDLE; end if; when READ_DATA => CS <= '0'; SYNC <= '1'; cnt <= cnt + 1; if (cnt<4) then cnt <= cnt + 1; state <= READ_DATA; elsif (cnt > 3 and cnt < 16) then cnt <= cnt + 1; -- the first 4 bits are 0000 only read the last 12 data(15-cnt) <= DIN; state <= READ_DATA; elsif (cnt = 16) then cnt <= 0; state <= FUNC; end if; -- signal processing would go in this state -- but for now we don't do anything in here when FUNC => CS <= '1'; SYNC <= '1'; cnt <= 0; state <= WRITE_DATA; when WRITE_DATA => CS <= '1'; SYNC <= '0'; if (cnt = 0 or cnt = 1) then cnt <= cnt + 1; DOUT <= '0'; state <= WRITE_DATA; elsif (cnt = 2 or cnt = 3) then cnt <= cnt + 1; DOUT <= '0'; state <= WRITE_DATA; elsif (cnt > 3 and cnt < 16) then cnt <= cnt + 1; DOUT <= data(15 - cnt); state <= WRITE_DATA; elsif (cnt = 16) then cnt <= 0; state <= IDLE; end if; end case; end if; end if; end process main; ibufgds_0 : IBUFGDS port map ( I => SCLK_P, IB => SCLK_n, O => CLK ); end Behavioral; Do you have an idea?
  12. Hello Guys! I hope you can help me with some doubts. I have a code that I use the ADC, TIMER and ETHERNET modules, when I try to compile it some erros are reported, as follows: C:/Users/MyName/Desktop/mpide-0023-windows-20140821/hardware/pic32/compiler/pic32-tools/bin/../lib/gcc/pic32mx/4.5.2/../../../../pic32mx/bin/ld.exe: small-data section exceeds 64KB; lower small-data size limit (see option -G) chipKITEthernet\utility\DNS.c.o: In function `DNSEndUsage': C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:208:(.text.DNSEndUsage+0x0): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:211:(.text.DNSEndUsage+0x20): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:213:(.text.DNSEndUsage+0x38): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' chipKITEthernet\utility\DNS.c.o: In function `DNSResolve': C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:262:(.text.DNSResolve+0x48): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:256:(.text.DNSResolve+0x74): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' chipKITEthernet\utility\DNS.c.o: In function `DNSIsResolved': C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:358:(.text.DNSIsResolved+0x0): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:369:(.text.DNSIsResolved+0xac): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:380:(.text.DNSIsResolved+0xfc): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:384:(.text.DNSIsResolved+0x114): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:388:(.text.DNSIsResolved+0x124): relocation truncated to fit: R_MIPS_GPREL16 against `no symbol' C:/Users/MyName/Documents/mpide/libraries/chipKITEthernet/utility/DNS.c:423:(.text.DNSIsResolved+0x1f4): additional relocation overflows omitted from the output collect2: ld returned 1 exit status I'm using the timer with interruption enabled, the ADC is used to scan 6 chs and the Ethernet to send the data to my computer, somebody coud help me? Regards.
  13. Hi there, I recently purchased a Zybo Zynq 7000 development board and have been working through tutorials to familiarize myself with Vivado, IP blocks, etc (not a ton of experience with FPGAs). I have used the base system design included and successfully was able to display images from the HDMI out on the board using an included demo. For the project I have in mind, however, I really want the HDMI port to function as a receive/sink port rather than transmit/source. All the other peripherals configured in the base system design are perfect for my application aside from the HDMI. Is there a way to change the base system design to have the HDMI configured as receive rather than transmit? Or can someone direct me as to how to configure an IP block in Vivado for HDMI receive for the Zybo? I have no experience with Vivado or IP blocks or p cores or what have you, and while I have a basic understanding how the design flow in Vivado,a guide with beginners in mind would be appreciated. This next part may sound dumb, but is just an idea: while looking through the schematic for the HDMI port, it seems that there is an HDMI_OEN pin (hdmi output enable?), and in Vivado a similar block that says HDMI_OEN is present above the IP block for the HDMI TX. Is it as simple as flipping the value on the HDMI_OEN pin? I feel that is too simple too work but just thought I'd include the info anyways in case it is useful or relevant. Thanks, Chris
  14. Hi All, I am using the HS2 to drive ARC based system through the metaware debugger. Some target require low speed communication so I use metaware speed reduction switch -prop=dig_speed which must be translated to some Digilent speed settings call. The issue is that although the speed gets globally reduced, looking on the scope, one can see short TCK pulses of 200ns, irrespective of the speed settings, inserted in an otherwise reduced clock signal. Even at speed as low as 200KHz this issue remains. This causes target attach failure. Picture describing the issue is attached. I downloaded the latest runtime on digilent support site but still getting old drivers signature: ===== Digilent Adept ===== Adept System Rev 2.7 Adept Runtime Rev 2.16 Adept Application Rev 2.4.2 Copyright © 2010 Is this expected, any new drivers available ? Are there some workaround to fix the issue ? We acquired a large number of HS2 so fixing this issue is crucial for us. Best regards, Serge
  15. Hi all,I have a Zybo Zynq 7000 and have been working on a custom design in Vivado 2014.4 which uses the VDMA IP core. I want to access the data stored in the VDMA in Linux userspace and am using embedded Linux (a Ubuntu 12.04 distribution). I have generated a device tree for the design and have verified that Linux recognizes the VDMA as a device (it is listed in /sys/bus/platform/devices).My question now is how to actually use the VDMA? I've been reading around on the forums and online and see that you must either use the Xilinx VDMA driver for Linux or use mmap, but many people reccomend using the driver instead of mmap.There does not seem to be a lot of documentation on the VDMA driver, so I was wondering if anyone could help me out with how to install/configure the VDMA driver and use it? I found this http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs#AXI%20VDMA but it is very brief. It mentions it can be configured through menuconfig but it does not explain how to do that. I am very new to Linux and have no experience with menuconfig but from what I've read I can mess up a lot of things if I don't know what I am doing with menuconfig.Can anyone show me how or point me towards a good guide or tutorial for configuring and using the VDMA driver,or Linux drivers in general?Thank you,Chris
  16. Hi all, I am trying to work on "Embedded Linux Hands-on Tutorial -- ZedBoard" .pdf document avilable in "http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,1028&Prod=Z... ". This doc. says get design named as "ZedBoard Linux Hardware Design" from same link, and it is having support for "ISE 14.4" and not for "Vivado", how to use the same ISE design in vivado or there is seperate degin for Vivado? My understnding is Vivado is replacement of ISE design suite. Cna you please brief me the procedure , how I can change ISE Design suite into Vivado Design Suite(Any prefered Document whcih we can follow), because lot of Design examples are not supporting Vivado, I am working on these designs, if I get any Document I wil work on it and post the same to all. Thanks & Regards Satish.G
  17. Jnadin

    Jtag HS3

    Hi All, I am having issues using the JTAG HS3 with my PCB that uses zynq 7020 chip. I have tried using it with zc702 and zedboard and these seems to work however plugging the device into my board the device is not found. I am guess there is something I have missed when designing the board. I have the lines pulled high to 3V3 which then go to the FPGA. Is there any thing else I need to consider for the PCB to work with this device? was anyone able to design a board that had this JTAG working? Kind Regards, J. Nadin
  18. hi to all, I am using NETFPGA-1G-CML. I have ported Linux in it and it is working fine.Now i have enable three Ethernet ports. PC --------------------> Board1 (ETH0) 192.168.1.1 192.168.1.2 I have connected my PC to NETFPGA board via telnet. Board1 (ETH1) ----------------> RF Device -------------- Wireless Medium ----------------- RF Device --------------- Board2 (ETH1) 192.168.2.66 192.168.2.67 192.168.2.68 192.168.2.69 Now i can ping from 192.168.2.66 to 192.168.2.67 & 192.168.2.68 but cant ping 192.168.2.69 Now when i remove NETFPGA board and put my laptop on one end and set up same ethernet ip. In this i can easily ping from 192.168.2.66 to 192.168.2.69. Please help me in this regard, very greatful to you. Regards,
  19. I’m a PhD student working in a mechanics laboratory in France (LMT Cachan) and one of the goals of my thesis is to control a hydraulic testing machine using digital image correlation techniques. In order to do this, I need to take a photo of a sample, process it, extract 4 parameters and send them to the testing machine. This process needs to be repeated at a frequency of approximately 80Hz. We need a device to send these values from a Linux computer to the 4 analog entries of the machine (0-10V, 0.5 mA) by coaxial BNC cable. We managed to do this for one channel using an USB connected oscilloscope by sending a continuous current by changing the offset using C++. The problem is that this solution is too slow and has only one channel. For this we would need a device that has a viable and fast connection (Ethernet, PCI, even USB if recommended) that can send data from a Linux computer (ideally using C++) with a latency of around 1ms, frequency of at least 100Hz, precision of 0.1% and on 4 synchronized analog outputs. Given that I am not particularly specialized in the field of electronics, researching such a device among the large quantity of items produced by your firm proves to be a difficult task. I would like to know if you have a product that fits our needs and if similar purpose programming has already been done (or could easily be done) to send data from a linux computer to analog outputs (using C++ ideally). Best regards, Ionut Prisacari
  20. Hi all I'm still using a Spartan3e starter kit for various issues (it's aged but still very usefull). For my current project i need to program the Spartan using an external uP that i want to connect to the connector for extended JTag (J28). Now i become unsecure how this should work. The s3e1600 board provides an integrated JTag programmer. Unfortunally it is not documented in the schematic's since it is an Xilinx proprietary design. Moreover J28 does not provide anything like the PGND signal, found i.e. at the Xilinx platform cable USB II. Hence the S3e1600 board can't detect a connected JTag adapter. I ask myself if this cause any problems when i now use a second (!) JTAG master (via J28) to drive the JTag chain. If i interpret the given schematics correct then i would assume that the integrated JTag controller would be in parallel to J28 (but as i said: this is not documented) which would be asking for trouble . Can anyone provide some help for this ? Thanks in advance Regards AHz
  21. The websites for the chipKIT Max32 and Network Shield both list multiple revisions of schematic (D vs E for the Max32; D vs F for the Network Shield). Both websites, however, only list a single orderable part number. What revision / version of hardware am I ordering? To add to the confusion, I called Digilent today and the sales gal confirmed with shipping that both units are only shipping revision C. ???
  22. Hi, I went through the MPLAB X IDE tutorial. I then changed the product properties to suit my device (PIC32MZ2048ECG100) and debugger (Chipkit PGM). I also changed the port to PortB where user-LED 3 is connected (RB11). When I debug using Simulator, the variables change as they should. However when I program the device, LED3 does not light up as it should. So I also added ANSELB =0 statement to make it a digital port. But still nothing happens. I have exhausted all possible causes I could think of. I would appreciate any ideas. Below is the code, Thanks. #include <xc.h> #pragma config FWDTEN = OFF, JTAGEN = OFF void delay(void); unsigned int ctr = 0; unsigned int delayVal = 2048; int main(void) { LATB= 0; //LED 3 is connected to RB11 TRISB = 0x0000; //set the lower sixteen bits of a port as output ports by //setting the lower eight bits to zero ANSELB=0; //set port B as digital while(1) //infinite loop { LATB = 0b0000000000000000; // assigns 0 to the lower 11th bit of LATB register delay(); LATB = 0b0000100000000000; // assigns to the lower 11th bit of LATB register delay(); ctr++; } } void delay(void) //controls the amount of time that the values appear { unsigned int i,j; for (i = 0; i < delayVal; i++) { for (j = 0; j < 20; j++); } } /********************************************************************** * © 2013 Microchip Technology Inc. * SOFTWARE LICENSE AGREEMENT: * Microchip Technology Inc. (Microchip) licenses this software to you * solely for use with Microchip dsPIC digital signal controller * products. The software is owned by Microchip and is protected under * applicable copyright laws. All rights reserved. * * SOFTWARE IS PROVIDED AS IS. MICROCHIP EXPRESSLY DISCLAIMS ANY * WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A * PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL MICROCHIP * BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL * DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF * PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS * BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), * ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. **********************************************************************/
  23. yasirshah

    Vmodcam resolution

    I am using Digilent Atlys board and Vmodcam in a project. Vmodcam have 1600*1200 maximum resolution. it can be used with 640*480 resolution. I want to know that what is the minimum resolution of Vmodcam. Can it be used for 300*200 resolution?
  24. endluri.ram

    Pmod Doubt in ZYBO

    Hi, I am using PS and custom IPs to do a IR remote demodulation project. I need IR signal from external circuit. My custom IR Demodulator IP does the work and displays the message received. I need to use one of the Pmod banks. My question is can I use standard/ Hi-speed Pmod bank or am I only allowed to use MIO Pmod to receive the input? Also when we generate custom IP we get a signal S_AXI_ACLK signal as clock. How can I find the frequency of this clock signal? Thank You
  25. I bought a Nexys™4 Artix-7 FPGA a while ago and I turned it on today. I was waiting for the user demo that comes pre-installed to say PASS but instead this time is says "Fail 2" "see doc". what does this mean? I cant find this anywhere in the document at all. Thanks alex