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Found 105 results

  1. Hello, I'm trying to get http://www.digilentinc.com/Data/Products/ATLYS/Atlys_AXI_Web_Server_Demo_v_1_02.zip to work on my Atlys board but I'm running into errors in SDK. After I clean & build, the elfcheck passes: 10:39:52 **** Incremental Build of configuration Debug for project Atlys_Webserver_Demo **** make all 'Building file: ../src/additional_sf_ops.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/additional_sf_ops.d" -MT"src/additional_sf_ops.d" -o "src/additional_sf_ops.o" "../src/additional_sf_ops.c" ../src/additional_sf_ops.c: In function 'hchartoi': ../src/additional_sf_ops.c:837:5: warning: array subscript has type 'char' [-Wchar-subscripts] ../src/additional_sf_ops.c:843:5: warning: array subscript has type 'char' [-Wchar-subscripts] 'Finished building: ../src/additional_sf_ops.c' ' ' 'Building file: ../src/dispatch.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/dispatch.d" -MT"src/dispatch.d" -o "src/dispatch.o" "../src/dispatch.c" ../src/dispatch.c: In function 'print_headers': ../src/dispatch.c:31:9: warning: implicit declaration of function 'print_echo_app_header' [-Wimplicit-function-declaration] ../src/dispatch.c:34:9: warning: implicit declaration of function 'print_rxperf_app_header' [-Wimplicit-function-declaration] ../src/dispatch.c:37:9: warning: implicit declaration of function 'print_txperf_app_header' [-Wimplicit-function-declaration] ../src/dispatch.c:40:9: warning: implicit declaration of function 'print_tftp_app_header' [-Wimplicit-function-declaration] ../src/dispatch.c:43:9: warning: implicit declaration of function 'print_web_app_header' [-Wimplicit-function-declaration] ../src/dispatch.c: In function 'start_applications': ../src/dispatch.c:52:9: warning: implicit declaration of function 'start_echo_application' [-Wimplicit-function-declaration] ../src/dispatch.c:55:9: warning: implicit declaration of function 'start_rxperf_application' [-Wimplicit-function-declaration] ../src/dispatch.c:58:9: warning: implicit declaration of function 'start_txperf_application' [-Wimplicit-function-declaration] ../src/dispatch.c:61:9: warning: implicit declaration of function 'start_tftp_application' [-Wimplicit-function-declaration] ../src/dispatch.c:64:9: warning: implicit declaration of function 'start_web_application' [-Wimplicit-function-declaration] ../src/dispatch.c: In function 'transfer_data': ../src/dispatch.c:71:9: warning: implicit declaration of function 'transfer_echo_data' [-Wimplicit-function-declaration] ../src/dispatch.c:74:9: warning: implicit declaration of function 'transfer_rxperf_data' [-Wimplicit-function-declaration] ../src/dispatch.c:77:9: warning: implicit declaration of function 'transfer_txperf_data' [-Wimplicit-function-declaration] ../src/dispatch.c:80:9: warning: implicit declaration of function 'transfer_tftp_data' [-Wimplicit-function-declaration] ../src/dispatch.c:83:9: warning: implicit declaration of function 'transfer_web_data' [-Wimplicit-function-declaration] ../src/dispatch.c:84:1: warning: control reaches end of non-void function [-Wreturn-type] ../src/dispatch.c: In function 'start_applications': ../src/dispatch.c:65:1: warning: control reaches end of non-void function [-Wreturn-type] 'Finished building: ../src/dispatch.c' ' ' 'Building file: ../src/echo.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/echo.d" -MT"src/echo.d" -o "src/echo.o" "../src/echo.c" 'Finished building: ../src/echo.c' ' ' 'Building file: ../src/http_response.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/http_response.d" -MT"src/http_response.d" -o "src/http_response.o" "../src/http_response.c" ../src/http_response.c: In function 'do_delete_file': ../src/http_response.c:529:12: warning: unused variable 'fd' [-Wunused-variable] ../src/http_response.c: In function 'do_list_file': ../src/http_response.c:729:4: warning: 'return' with no value, in function returning non-void [-Wreturn-type] ../src/http_response.c: In function 'do_http_get': ../src/http_response.c:868:4: warning: 'return' with no value, in function returning non-void [-Wreturn-type] ../src/http_response.c: In function 'data_receive_callback': ../src/http_response.c:353:5: warning: 'pcb' may be used uninitialized in this function [-Wuninitialized] ../src/http_response.c: In function 'do_download_file': ../src/http_response.c:459:7: warning: 'buf' may be used uninitialized in this function [-Wuninitialized] 'Finished building: ../src/http_response.c' ' ' 'Building file: ../src/main.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/main.d" -MT"src/main.d" -o "src/main.o" "../src/main.c" ../src/main.c: In function 'main': ../src/main.c:85:2: warning: implicit declaration of function 'lwip_init' [-Wimplicit-function-declaration] ../src/main.c:96:2: warning: implicit declaration of function 'platform_enable_interrupts' [-Wimplicit-function-declaration] ../src/main.c:116:3: warning: implicit declaration of function 'get_switch_state' [-Wimplicit-function-declaration] ../src/main.c:117:3: warning: implicit declaration of function 'get_pushbutton_state' [-Wimplicit-function-declaration] 'Finished building: ../src/main.c' ' ' 'Building file: ../src/platform.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform.d" -MT"src/platform.d" -o "src/platform.o" "../src/platform.c" ../src/platform.c: In function 'timer_callback': ../src/platform.c:50:2: warning: implicit declaration of function 'tcp_fasttmr' [-Wimplicit-function-declaration] ../src/platform.c:54:3: warning: implicit declaration of function 'tcp_slowtmr' [-Wimplicit-function-declaration] ../src/platform.c: In function 'xadapter_timer_handler': ../src/platform.c:62:11: warning: unused variable 'tcsr' [-Wunused-variable] ../src/platform.c:61:12: warning: unused variable 'timer_base' [-Wunused-variable] ../src/platform.c: In function 'init_platform': ../src/platform.c:257:2: warning: implicit declaration of function 'platform_init_fs' [-Wimplicit-function-declaration] 'Finished building: ../src/platform.c' ' ' 'Building file: ../src/platform_fs.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform_fs.d" -MT"src/platform_fs.d" -o "src/platform_fs.o" "../src/platform_fs.c" 'Finished building: ../src/platform_fs.c' ' ' 'Building file: ../src/platform_gpio.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/platform_gpio.d" -MT"src/platform_gpio.d" -o "src/platform_gpio.o" "../src/platform_gpio.c" 'Finished building: ../src/platform_gpio.c' ' ' 'Building file: ../src/prot_malloc.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/prot_malloc.d" -MT"src/prot_malloc.d" -o "src/prot_malloc.o" "../src/prot_malloc.c" ../src/prot_malloc.c: In function 'prot_mem_free': ../src/prot_malloc.c:39:1: warning: control reaches end of non-void function [-Wreturn-type] 'Finished building: ../src/prot_malloc.c' ' ' 'Building file: ../src/rxperf.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/rxperf.d" -MT"src/rxperf.d" -o "src/rxperf.o" "../src/rxperf.c" 'Finished building: ../src/rxperf.c' ' ' 'Building file: ../src/tftpserver.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/tftpserver.d" -MT"src/tftpserver.d" -o "src/tftpserver.o" "../src/tftpserver.c" ../src/tftpserver.c:57:8: warning: type defaults to 'int' in declaration of 'tftp_server_started' [-Wimplicit-int] ../src/tftpserver.c: In function 'tftp_process_read': ../src/tftpserver.c:191:13: warning: unused variable 'block' [-Wunused-variable] ../src/tftpserver.c:191:10: warning: unused variable 'n' [-Wunused-variable] ../src/tftpserver.c: In function 'tftp_process_write': ../src/tftpserver.c:276:13: warning: unused variable 'block' [-Wunused-variable] ../src/tftpserver.c:276:10: warning: unused variable 'n' [-Wunused-variable] ../src/tftpserver.c: In function 'start_tftp_application': ../src/tftpserver.c:406:1: warning: control reaches end of non-void function [-Wreturn-type] 'Finished building: ../src/tftpserver.c' ' ' 'Building file: ../src/tftputils.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/tftputils.d" -MT"src/tftputils.d" -o "src/tftputils.o" "../src/tftputils.c" 'Finished building: ../src/tftputils.c' ' ' 'Building file: ../src/txperf.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/txperf.d" -MT"src/txperf.d" -o "src/txperf.o" "../src/txperf.c" 'Finished building: ../src/txperf.c' ' ' 'Building file: ../src/urxperf.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/urxperf.d" -MT"src/urxperf.d" -o "src/urxperf.o" "../src/urxperf.c" 'Finished building: ../src/urxperf.c' ' ' 'Building file: ../src/utxperf.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/utxperf.d" -MT"src/utxperf.d" -o "src/utxperf.o" "../src/utxperf.c" ../src/utxperf.c: In function 'transfer_utxperf_data': ../src/utxperf.c:37:6: warning: unused variable 'copy' [-Wunused-variable] 'Finished building: ../src/utxperf.c' ' ' 'Building file: ../src/web_utils.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/web_utils.d" -MT"src/web_utils.d" -o "src/web_utils.o" "../src/web_utils.c" 'Finished building: ../src/web_utils.c' ' ' 'Building file: ../src/webserver.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/webserver.d" -MT"src/webserver.d" -o "src/webserver.o" "../src/webserver.c" ../src/webserver.c: In function 'http_sent_callback': ../src/webserver.c:86:13: warning: implicit declaration of function 'mfs_file_read' [-Wimplicit-function-declaration] ../src/webserver.c:91:17: warning: implicit declaration of function 'mfs_file_close' [-Wimplicit-function-declaration] ../src/webserver.c: In function 'http_recv_callback': ../src/webserver.c:115:3: warning: 'return' with no value, in function returning non-void [-Wreturn-type] ../src/webserver.c:117:3: warning: 'return' with no value, in function returning non-void [-Wreturn-type] ../src/webserver.c: In function 'start_web_application': ../src/webserver.c:158:2: warning: implicit declaration of function 'platform_init_gpios' [-Wimplicit-function-declaration] 'Finished building: ../src/webserver.c' ' ' 'Building file: ../src/xquad_spi.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/xquad_spi.d" -MT"src/xquad_spi.d" -o "src/xquad_spi.o" "../src/xquad_spi.c" 'Finished building: ../src/xquad_spi.c' ' ' 'Building target: Atlys_Webserver_Demo.elf' 'Invoking: MicroBlaze gcc linker' mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../standalone_bsp_0/microblaze_0/lib -mlittle-endian -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.40.b -mno-xl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "Atlys_Webserver_Demo.elf" ./src/additional_sf_ops.o ./src/dispatch.o ./src/echo.o ./src/http_response.o ./src/main.o ./src/platform.o ./src/platform_fs.o ./src/platform_gpio.o ./src/prot_malloc.o ./src/rxperf.o ./src/tftpserver.o ./src/tftputils.o ./src/txperf.o ./src/urxperf.o ./src/utxperf.o ./src/web_utils.o ./src/webserver.o ./src/xquad_spi.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group -Wl,--start-group,-lxil,-llwip4,-lgcc,-lc,--end-group 'Finished building target: Atlys_Webserver_Demo.elf' ' ' 'Invoking: MicroBlaze Print Size' mb-size Atlys_Webserver_Demo.elf |tee "Atlys_Webserver_Demo.elf.size" text data bss dec hex filename 172996 1552 34190284 34364832 20c5da0 Atlys_Webserver_Demo.elf 'Finished building: Atlys_Webserver_Demo.elf.size' ' ' 'Invoking: Xilinx ELF Check' elfcheck Atlys_Webserver_Demo.elf -hw ../../hw_platform/system.xml -pe microblaze_0 |tee "Atlys_Webserver_Demo.elf.elfcheck" elfcheck Xilinx EDK 14.7 Build EDK_P.20131013 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Command Line: elfcheck -hw ../../hw_platform/system.xml -pe microblaze_0 Atlys_Webserver_Demo.elf ELF file : Atlys_Webserver_Demo.elf elfcheck passed. 'Finished building: Atlys_Webserver_Demo.elf.elfcheck' ' ' 10:40:03 Build Finished (took 11s.626ms) However when I click program FPGA, I get elfcheck -hw C:/Users/C16Evan.Richter/Desktop/microBlaze/final_project/hw_platform/system.xml -mode bootload -mem BRAM -pe microblaze_0 C:/Users/C16Evan.Richter/Desktop/microBlaze/final_project/Atlys_Webserver_Demo/Debug/Atlys_Webserver_Demo.elf elfcheck Xilinx EDK 14.7 Build EDK_P.20131013 Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Command Line: elfcheck -hw C:/Users/C16Evan.Richter/Desktop/microBlaze/final_project/hw_platform/system.xml -mode bootload -mem BRAM -pe microblaze_0 C:/Users/C16Evan.Richter/Desktop/microBlaze/final_project/Atlys_Webserver_Demo/D ebug/Atlys_Webserver_Demo.elf ELF file : C:/Users/C16Evan.Richter/Desktop/microBlaze/final_project/Atlys_Webserver_Demo/D ebug/Atlys_Webserver_Demo.elf ERROR:EDK:3165 - elfcheck failed! The following sections did not fit into Processor BRAM memory: Section .data (0xC002A3D0 - 0xC002A9CF) Section .rodata (0xC0027D04 - 0xC002A3CB) Section .dtors (0xC0027CFC - 0xC0027D03) Section .ctors (0xC0027CF4 - 0xC0027CFB) Section .fini (0xC0027CD4 - 0xC0027CF3) Section .init (0xC0027C98 - 0xC0027CD3) Section .text (0xC0000000 - 0xC0027C97) Try using the linker script generation tools to generate an ELF that maps correctly to your hardware design. Programming the FPGA failed due to errors from elfcheck My lscript.ld file is as follows: /*******************************************************************/ /* */ /* This file is automatically generated by linker script generator.*/ /* */ /* Version: Xilinx EDK 14.3 EDK_P.40xd */ /* */ /* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */ /* */ /* Description : MicroBlaze Linker Script */ /* */ /*******************************************************************/ _STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x1000000; _HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x1000000; /* Define Memories in the system */ MEMORY { microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl : ORIGIN = 0x00000050, LENGTH = 0x00007FB0 mcb_ddr2_S0_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x08000000 } /* Specify the default entry point to the program */ ENTRY(_start) /* Define the sections, and where they are mapped in memory */ SECTIONS { .vectors.reset 0x00000000 : { *(.vectors.reset) } .vectors.sw_exception 0x00000008 : { *(.vectors.sw_exception) } .vectors.interrupt 0x00000010 : { *(.vectors.interrupt) } .vectors.hw_exception 0x00000020 : { *(.vectors.hw_exception) } .text : { *(.text) *(.text.*) *(.gnu.linkonce.t.*) } > mcb_ddr2_S0_AXI_BASEADDR .init : { KEEP (*(.init)) } > mcb_ddr2_S0_AXI_BASEADDR .fini : { KEEP (*(.fini)) } > mcb_ddr2_S0_AXI_BASEADDR .ctors : { __CTOR_LIST__ = .; ___CTORS_LIST___ = .; KEEP (*crtbegin.o(.ctors)) KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) __CTOR_END__ = .; ___CTORS_END___ = .; } > mcb_ddr2_S0_AXI_BASEADDR .dtors : { __DTOR_LIST__ = .; ___DTORS_LIST___ = .; KEEP (*crtbegin.o(.dtors)) KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) PROVIDE(__DTOR_END__ = .); PROVIDE(___DTORS_END___ = .); } > mcb_ddr2_S0_AXI_BASEADDR .rodata : { __rodata_start = .; *(.rodata) *(.rodata.*) *(.gnu.linkonce.r.*) __rodata_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .sdata2 : { . = ALIGN(8); __sdata2_start = .; *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) . = ALIGN(8); __sdata2_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .sbss2 : { __sbss2_start = .; *(.sbss2) *(.sbss2.*) *(.gnu.linkonce.sb2.*) __sbss2_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .data : { . = ALIGN(4); __data_start = .; *(.data) *(.data.*) *(.gnu.linkonce.d.*) __data_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .got : { *(.got) } > mcb_ddr2_S0_AXI_BASEADDR .got1 : { *(.got1) } > mcb_ddr2_S0_AXI_BASEADDR .got2 : { *(.got2) } > mcb_ddr2_S0_AXI_BASEADDR .eh_frame : { *(.eh_frame) } > mcb_ddr2_S0_AXI_BASEADDR .jcr : { *(.jcr) } > mcb_ddr2_S0_AXI_BASEADDR .gcc_except_table : { *(.gcc_except_table) } > mcb_ddr2_S0_AXI_BASEADDR .sdata : { . = ALIGN(8); __sdata_start = .; *(.sdata) *(.sdata.*) *(.gnu.linkonce.s.*) __sdata_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .sbss (NOLOAD) : { . = ALIGN(4); __sbss_start = .; *(.sbss) *(.sbss.*) *(.gnu.linkonce.sb.*) . = ALIGN(8); __sbss_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .tdata : { __tdata_start = .; *(.tdata) *(.tdata.*) *(.gnu.linkonce.td.*) __tdata_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .tbss : { __tbss_start = .; *(.tbss) *(.tbss.*) *(.gnu.linkonce.tb.*) __tbss_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .bss (NOLOAD) : { . = ALIGN(4); __bss_start = .; *(.bss) *(.bss.*) *(.gnu.linkonce.b.*) *(COMMON) . = ALIGN(4); __bss_end = .; } > mcb_ddr2_S0_AXI_BASEADDR _SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); _SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); /* Generate Stack and Heap definitions */ .heap (NOLOAD) : { . = ALIGN(8); _heap = .; _heap_start = .; . += _HEAP_SIZE; _heap_end = .; } > mcb_ddr2_S0_AXI_BASEADDR .stack (NOLOAD) : { _stack_end = .; . += _STACK_SIZE; . = ALIGN(8); _stack = .; __stack = _stack; } > mcb_ddr2_S0_AXI_BASEADDR _end = .; } I have not modified any files given in the demo. Can someone please help me figure out what to do so that the project compiles and can be programmed on my Atlys board? Thanks
  2. Hi, I want to create an AXI Memory Mapped Master from a custom IP which can read/write off-chip memory. I would like to use this IP in my Vivado block design. Target platform is: Nexys4DDR board with xc7a100tcsg324-1 FPGA. I use Vivado 2014.4 under Win7 64 bit. I have made the Gettig started with Microblaze guide (https://reference.digilentinc.com/nexys4-ddr:gsmb). Everything went fine, now I have a Vivado block design with Microblaze, Uart, MIG, and some other peripherals. I have also set the master.xdc file, and I can generate the bitfile. SDK template tests (hello world, memory test) also passed successfully. I have a custom made IP, from which I would like to make an AXI MM Master peripheral, and I want to control (read/write) the DDR2 memory from my custom made IP. I have created a new AXI4 peripheral with the Create or Package IP wizard in Vivado. I have choosen the following interface: Interface Type: Full Interface Mode: Master Data Width (Bits): 32 After clicking Finish, Vivado creates a new peripheral in which I can intantiate my custom IP. However this generated myip_v1_0_M00_AXI.vhd looks a little bit hard to understand for me. I haven't even find any Read/Write ports amongst the interface ports. Basically what do I need to control from my custom IP? I assume the M_AXI_AWADDR, M_AXI_WDATA, M_AXI_ARADDR and M_AXI_RDATA ports for address and data, but what about read/write etc? I have found tons of tutorials on the web about how to make an AXI Lite Slave interfaced IP, but I couldn't find any reference designs for AXI Memory Mapped Master. Could you please post me some examples or helping by making comments in my file attached? Thanks! Shodan
  3. Hi I am new here. My background is I used ISE 10 but mainly used the schematic capture and the FSM software for my designs. I used a little VHDL and Verilog from the library to form some blocks for my schematic projects. For the most part my designs have all centered on Schematics. I have some unique design blocks for full projects I did with the finite State machine software. I have in stock has a Nexys 2 board with a Spartan 3500E on it and I was planning to use for a demo model when I found out this board is being discontinued. I like the 7A100 you have on the Nexys 4. This will multiply my capabilities compared the old board I had. I also downloaded the Vivado series design tool and found it very powerful in some aspects to ISE. I lost my connection to someone that can write code and Tcl script. I need to get this demonstration model done ASAP so I have the following questions. I see you cannot migrate schematic files to Vivado. I don’t want to migrate complete projects just the blocks of circuits in them especially the ones I generated from the FSM software which is converted to VHDL and Verilog. Can I make custom IP’s from them and use them in Vivado? Are there files I can take from my old ISE project circuit blocks and can use in my IP catalog and Vivado? In the IP catalog I don’t see some circuits I need in my design.I don’t have time for a learning curve. Is the Vivado software a software that requires more knowledge and experience concerning writing code than I have (which is limited)? If I can handle the learning curve using the Vivado design tools in a descent amount of time, I want to use the Nexys 4 with 7A100 in it. If I can’t then I will have to use the Nexys 2 board that has. the Spartan 3500EWhat kind of prerequisites in learning do I need to perform a successful project in Vivado?Thanks Rex
  4. Greetings, New user to the forum, hope I can contribute some in the not so distant future. I am here by the recommendation of Digilent technical support. I am the new owner of a suspected malfunctioning Dev board (Genesys / Xilinx ) . Perhaps someone out there has some on hands experience with this particular product? I am having difficulty getting a power good indication (LD8) when I apply the required 5V supply. For a short time I have been exploring the Adept interface in an attempt to communicate with the board and when using the Power meter I notice the various voltages along with respected currents seem to be okay except the 2.5 V output indicates around 2 Volts and shows around -8 to -10 mA current. To me, this suggest no 2.5 V supply being generated by the switch mode power supply, are there any suggestions what to look for? So far, I have not had much success with email support in this matter. I really would like to get upto speed so I can contribute to the FPGA development community. Thank you in advance, J.L. Moon
  5. endluri.ram

    Reset Button on ZYBO

    I am using ZYBO board. I am running microblaze processor to use GPIO block. Microblaze need two reset buttons. How can I connect those two buttons to the onboard reset buttons 'BTN7 : PS-SRST' and 'BTN6 PROGB'? I cannont find pin number in master XDC file. I can connect reset to push buttons but i will be losing two buttons for that purpose.
  6. Hello, I have successfully programmed my Basys2 using the 'djtgcfg' utility under Linux dozens of times, but I'm no longer able to do so. When I attempted to program the board yesterday, I got some unusual results: > djtgcfg enum Device: 3.....O......<. Product Name: Digilent Basys2-100 User Name: 3.....O......<. Serial Number: 210155528315 > djtgcfg init -d 'Basys2' ERROR: unable to open device "Basys2" > djtgcfg init -d '3.....O......<.' ERROR: unable to open device "3.....O......<." *I used the '.' character in the strings above to represent non-printable characters, because the replacement character used by my terminal won't display properly on this page. Using the product name or serial number yields a similar result. It appears that I can't communicate with the device due to a corrupted device ID. However, my computer has no trouble recognizing the Basys2 board: > lsusb ... Bus 003 Device 011: ID 1443:0007 Digilent Development board JTAG ...For what it's worth, here is the hexdump of the djtgcfg result above: > djtgcfg enum | xxd 0000000: 466f 756e 6420 3120 6465 7669 6365 2873 Found 1 device(s 0000010: 290a 0a44 6576 6963 653a 2033 fbbb b0df )..Device: 3.... 0000020: e04f a81f bdff bbf9 ec3c ad0a 2020 2020 .O.......<.. 0000030: 5072 6f64 7563 7420 4e61 6d65 3a20 2020 Product Name: 0000040: 4469 6769 6c65 6e74 2042 6173 7973 322d Digilent Basys2- 0000050: 3130 300a 2020 2020 5573 6572 204e 616d 100. User Nam 0000060: 653a 2020 2020 2020 33fb bbb0 dfe0 4fa8 e: 3.....O. 0000070: 1fbd ffbb f9ec 3cad 0a20 2020 2053 6572 ......<.. Ser 0000080: 6961 6c20 4e75 6d62 6572 3a20 2032 3130 ial Number: 210 0000090: 3135 3535 3238 3331 350a 155528315.So it appears the device ID as seen by djtgcfg is 33fb bbb0 dfe0 4fa8 1fbd ffbb f9ec 3cad 0aA couple of other details that might be helpful: I succesfully programmed a friend's Basys2 multiple times using djtgcfg after having this problem with my board. When using his board, the output from djtgcfg was normal (all printable characters).After experiencing this problem under Linux, I sucessfully programmed my Basys2 from a Windows machine. When using Adept2 under Windows, the device ID string still appears corrupted, but I am able to program it anyways. I don't have regular access to a Windows machine, so I'd really like to get this working under Linux again. I'm hoping this is just an issue of some corrupted Flash or EEPROM in the AT90USB that could be fixed by reprogramming it... but I'm not sure what to try next. Any ideas? Thanks for reading!
  7. Hi, I am just bought UDB and new with the PIC32 and was wondering if you can provide any example code or projects for the UDB. Cheers Paul
  8. I'm new to using the Diligent FPGA products and I have a question about how to use the Adept software with the Cmod S6 board. I would like to use Adept to transfer application data (24 bit pixel color values) from a PC disk file to my Cmod S6 FPGA application. I plan to implement the Diligent Parallel Interface Module Reference Design in my FPGA based on the DPIMREF.VHD example. My question is: Does the Adept software running on the PC require the data file to be in a specific format (such as EDIF) or can I send a binary file which is essentially a non-standard sequence of 8 bit data bytes in my own format to be processed by my FPGA application? Note that the file size could range from kilobytes up to a few Megabytes. Any help would be appreciated. Phil May
  9. Hi, I just bought the Chipkit Wi-Fire board and trying to use the DEIPcK examples that are provided on Digilent's website in MPIDE. However, when I try to compile an example program, for example WiFiScan, I get the following error message: WiFiScan.cpp:55:101: fatal error: MRF24G.h: No such file or directorycompilation terminated. MRF24G.h is the first h file that the program tries to load. I've included the DEIPcK libraries in the way that is described on this website: http://chipkit.net/started/learn-basics/party-libraries/ Any suggestions?
  10. Hello. I am working with an Atlys board. I am trying to transfer a bitstream file and a linux image to the SPI flash. In windows I remember doing it from the flash tab in the Adept application. Now I am working on a linux computer and I've installed the Adept 2 runtime and utilities. I've read the man pages for the 3 utilities (dadutil, djtgcfg and dsumecfg) but it is still not clear to me if it is posible to transfer to SPI flash using these utilities. Is it?
  11. Jo-Jo

    Can't Program Zybo

    I'm new to FPGA work, but I think there is something wrong with the Zybo board I just received. Vivado tells me there are no debug cores. When I try to program it it says the debug core was not detected. I'm using the same project I used to program a different Zybo board, so I don't think it's the project configuration. I searched on the Vivado forum, and all I found was that this will happen if the JTAG clock frequency is less than the ILA clock frequency. I have no idea what that means. Vivado suggested I manually launch hw_server with some parameters specified. I tried that, but I still have the same issue. Can anyone here tell me how to get my board running? Or is this thing just broke?
  12. zygot

    Adept SDK

    The documentation for using the SDK software libraries and sample HDL is, let's go with sparse to be kind. I've been using it for a few years but my last project has resulted in unexpected behaviour. I have a design that uses both dpmiref and stmctrl sample HDL components and want to access both in my PC application. I don't get any errors, but when I execute DeppDisable() and then DstmEnable() I sometimes have the contents of epp registers lost. Then, when I try and do a DstmIOEX() transfer UsbStmen never gets asserted and the application hangs until the library code times out. I've done this in the past with success but just am not finding what's different in the current project that is causing me grief. Does Digilent have any useful examples (HDL and C code) using both synchronous an asynchronous USB data transfers in one design? Also, can I really do overlapped synchronous IO? The API suggests yes, the documentation and my experimentation no.
  13. Hi, I am currently using Zybo board. I have followed the " Embedded Linux® Hands-on Tutorial for the ZYBO™ " tutorial. My question is how does the Zynq system works? Is it similar to Microblaze soft processor or is it just FPGA? I have done the same work in the tutorial using Microblaze processor and XIlinx ISE. I find in the specs that Zynq hosts 2 ARM cortex processors, I want to know when we run above the above tutorial are we using any soft processor or if we are using the ARM Cortex processor? My point is if any soft processor is involved we can eliminate it and use the ARM processors so that we can achieve more speed. Thank you in advance.
  14. Hello Guys, I just wanted to run the initial Test Program, shipped with the Digilent Xilinx Spartan-6 (Atlys_Demo_BIST). So i connected power and a HDMI-Plug (HDMI-out of course) and booted the board, nothing happens. The screens stays black. Any ideas? I downloaded the .bin file and flashed the chip again to be sure the program is present. Regards
  15. nacnud

    HS1 Device Names

    Hi, This one may need Digilent input: I named my HS1 devices using the Adept suite, but I was unaware that the names seem to be "per windows user". So when I ran my automated tests, under a different account, things failed. Is there a way to "globally name" my HS1 devices. I have two on each box in my test farm. There are 7 boxes in the farm. Thank you, Duncan
  16. good morning the example Atlys_AXI_Web_Server_Demo_v_1_02.zip doesn't work on ise design suite 14.7. for the compilation and the programmation of the boards it's ok i have the message autonegociate 100Mb/s on the console but no dialog with the computer on the network the Library is lwip best regards
  17. Hi, I am trying to use the dpcutil.dll library with Visual .Net [C#]. I've managed to import the functions what I need to write and read registers in my BASYS2 EVB [250]. const string _dllLocation = "C:WindowsSystem32dpcutil.dll"; [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcInit(ref int perc); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern void DpcTerm(); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcGetDpcVersion(StringBuilder szVersion, ref int perc); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcOpenData(IntPtr phif, System.Text.StringBuilder szdvc, ref int perc, IntPtr ptrid); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcCloseData(IntPtr hif, ref int perc); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcPutReg(IntPtr hif, byte bAddr, byte bData, ref int perc, IntPtr ptrid); [DllImport(_dllLocation, CallingConvention = CallingConvention.Cdecl)] private static extern bool DpcGetReg(IntPtr hif, byte bAddr, ref byte pbData, ref int perc, IntPtr ptrid);I know that I am using correctly the dll because I get the dll version from the function DpcGetDpcVersion(). My problem is when I try to use the funciton DpcOpenData. I got the error number 3103. I've read in the Digilent Port Communications Programmers Reference Manual that: ercCantConnect: 3103. Description: Can’t connect to communication module. First of all I've recored the rom flash of the BASYS2 with the reference design: https://www.inf.pucrs.br/calazans/undergrad/laborg/mat_plataformas/Nexys2/dpimref.vhd In my DEV Visual .Net Application [C#]. I've been using the following steps: 1º.- DpcInit(ref theErc) -> theErc = 0 2º.- DpcGetDpcVersion(theVersion, ref theErc) -> theErc = 0 and theVersion =2.9.2 3º-. devCount = getDevCount() -> devCount = 2 4º.- for i= 0 to i < devCount => getDevName(i, devTemp); devTemp -> Basis2 AND devTemp -> Basis2_bis 5º.- DpcOpenData(hif, theDevice, ref theErc, ptrid) -> theErc = 3103 I am stacked in this step. Could you help me out how I can solve this problem? Thank you so much. Best regards.
  18. I've got the Nexys 3 board and it's reading some data from a peripheral, but I can't debug what's on the board because I'm not about to spend 600+ on chipscope. So I've thought about the possibility of using the UART to send data back to the PC to analyze there, but the problem is there's really just about zilch information out there on how to use the UART on this board. Let's be honest, the Digilent Nexys 3 user guide (pg 12) is absolutely useless in this regard. It explains what the UART does from a high level, and mentions using free FTDI drivers, but has absolutely no information whatsoever on how to actually use this feature. I've tried approaching this at a xilinx angle, searching for "UART cores", which are hard to find, potentially not free, and not simple to actually implement or use. (I managed to acquire a "XPS 16550 UART" license, but can't figure out the first thing about how to use it, since Xilinx loves to massively overcomplicate what should be simple instructions) So I'm abandoning that approach, and now I'm here. Shouldn't there be an easy way to get, this UART up and running?
  19. Hello All, I am a beginner in FPGA and to start with I want to sent the output of a 8 bit counter to the outside world through ethernet. My counter is working. Can anyone please send me any links or pdf or suggestions which can help me to send the data out of the FPGA through ethernet. Thanks James
  20. Squirrel

    ZYBO Board w/ XADC

    I was wondering if anyone had experience with the ZYBO board getting the XADC interface to work properly. I have the following diagram in Vivado 2014.4: <Vivado2014_4_Diagram.JPG> The associated XADC wizard settings are as follows: <XADC_Wizard1.JPG> <XADC_Wizard2.JPG> This lets me get the temperature from the XADC, but I am getting 'weird' values for XADC pairs 0-3 (which are hardwired to the XADC PMOD connector on the ZYBO); there doesn't appear to be a dependence on temperature though... here is AUX0, for example: <TempVsAUX0.JPG> In relation to VpVn (VpVn - AUXn) I observe for all 4 AUX channels: <WpWn_Minus_AUX.JPG> I'm not quite sure why AUX1 always agrees with VpVn, especially because they are sampled at different places in the C code... My source is as follows (null checks, comments, etc. removed for brevity): <XADC_Source.JPG> So, a few questions... 1) What is going on with the above? Anyone have any thoughts? 2) I didn't set up anything in the constraints (XDC) file for the XADC pins because I believe they are hardwired (and I get critical warnings when I do)... is this correct? 3) Are these the only four XADC inputs possible for the ZYBO (N/P pairs)? The wiring diagram seems to indicate this is the case... if it is, does anyone have a suggestion for an external ADC? Something well documented would be preferred.
  21. Hello guys, I'm working with Zybo SoC right now and I have a few questions which I couldn't find the answer anywhere. I am using petalinux in the card with the .bsp from digilent website (Petalinux 2014.2 Board Support Package). The thing is, I want to change/reprogram the PL many times but I want to do it from the Linux, e.g. using C program and configuration port /dev/xdevcfg. Is it possible to do it?When I use a command shell "cat <file-name>.bit > /dev/xdevcfg", I could reprogram the FPGA and I can see the result but I lost the control of the Linux. I couldn't access to the ARM via hyperterminal. Do you have any idea what cause this problem? Is that means when I reprogram the PL, I lose the PS part of the FPGA? Thank you very much for your response
  22. Hi, I see in the ZYBO_zynq_def.xml file the following: <Projinfo Part="xc7z010clg400-2" DeviceSize="xc7z010" Package="clg400" Speed="-2" /> However, on my ZYBO board I see the chip in the attached JPG file. (I attached the photo of the chip, because I had problems sharing a link. It says I can't use JPGs, is that right?) I think I have a speed grade 1 chip, but the ZYBO_zynq_def.xml file indicates speed grade 2. This appears to be a mis-match. Is the file correct? What am I missing here. Does this file run OK on my ZYBO revB board? Thanks for your patience! Cheers, David
  23. We have been using the JTAG-USB for years, and need to purchase a couple more programmers. Should we be considering the JTAG-HS2 instead? It seems to do everything the JTAG-USB does, but with a faster programming rate. We typically create SVF files using iMPACT, and then use Adept on the production floor to do the programming of Xilinx XC9572XL CPLDs. The JTAG-USB works fine, but if the JTAG-HS2 will program faster, but still works essentially the same, it would be worth trying. Also, any comments regarding the upcoming JTAG-HS3 in the context of this question? Thanks in advance! Paul
  24. Hi, I am interested in using a low cost digilent board in a low volume product. I would need to meet fcc ce requirements in order to sell this. I do not see any information about the digilent fpga boards and fcc ce compliance. Are any of the digilent boards compliant for fcc or ce? Thanks
  25. Can the Adept 2 software be silently installed in Windows from the command line?