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Found 11 results

  1. I recently moved my HDMI project from S7 to A7, and I am getting implementation warnings leading to bitstream errors. On the S7, I had to following setup // HDMI notes: we're using pmod JA. // for the S7: // top row is N14, M14, L18, L17 // bot row is N18, M18, M17, M16 // so TMDS1 is {L18, L17} = {hdmi_out_n[1], hdmi_out_p[1]} = green // so TMDS0 is {N14, M14} = {hdmi_out_n[0], hdmi_out_p[0]} = blue // so TMDS2 is {M17, M16} = {hdmi_out_n[2], hdmi_out_p[2]} = red // so CLOCK is {N18, M18} = {hdmi_out_n[3], hdmi_out_p[3]} where my constraints file has ## PMOD Header JA se
  2. I understand quite a few things have changed with the SDK to Vitis migration on the software side. But, I am having trouble with the hardware also I followed this tutorial and I get two error while trying to generate bitstream https://reference.digilentinc.com/learn/programmable-logic/tutorials/github-demos/start Any help is greatly appreciated. Thanks in advance The error message is as follows - [BD 41-1665] Unable to generate top-level wrapper HDL for the block design 'system.bd' is locked. Locked reason(s): * Block design contains locked IPs. Please run report_ip_stat
  3. xinx_92

    Arty S7 with Simulink

    Hello there, I´m not really new to FPGA because I'm used to program Xilinx FPGAs via System Generator on dSpace platforms. However I'm really new with out-of-the-box FPGA programming. I got myself an ARTY S7 development kit and i figured maybe it's also "easy" to deploy my Simulink models via Systems Generator on These FPGAs. But unfortunately I have no idea where to start. Does someone of you guys have experience with deploying Simulink models out of Vivado System Generator to the ARTY S7 board? Thanks in advance
  4. I'm working with a Xilinx Spartan-7 (Arty S7-25) FPGA and was wondering if the "P" and "N" for the PMOD differential pairs are reprogrammable or swappable? Will swapping them damage any components or just not work? I notice their naming scheme but is there any significance beyond that. The banks I'm referring to are the JA and JB PMOD connections (See JB bank below). Thank you!
  5. Hello, I am trying to implement LVDS (1.2V nominal) using the Digilent Arty-S7 25 board. The schematic shows that the JA and JB Pmod connectors have 4 diff. pairs per connector. However, it looks like VCCO (the power supply for this I/O bank) is tied to 3.3V. To my knowledge, there is no differential I/O protocol that uses 3.3V. Does this mean that JA and JB can't be used for differential pairs? (Wouldn't that negate the point of running the differential pairs in the first place?) Or do the pins just output the correct voltage when you implement the LVDS protocol? Please he
  6. Hi, Does Digilent Adept supports the boundary scan for ARTY S7, I want to verify the GPIO as I was able to do with Basys boards using digilent. If its possible with adept then how can I do that and if it is not possible then any other alternative that exists?
  7. I'm using the Arty A7-35 board and have been going through the tutorials and built a MicroBlaze soft processor with a UartLite serial port using Vivado 2018.3 on Ubuntu 18.04 LTS. It did not work! Looking through the Arty A7 Reference Manual I found this: and looking at this diagram: Then the Artix-7 A9 pin should be configured as an input and the D10 pin as output. But here is the usb_uart interface spec in the ./board_files/arty-a7-35/E.0/board.xml file : <interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart"
  8. tl;dr: If I use a 12v external power supply on my Arty-S7-50RevE can I use VIN (& GND) to power a 0.1A, 12v cpu fan? Longer: I'm having heat issues with my soft CPU on the S7 and so want to cool it before I take it multi-core. I've installed a heatsink (from here http://uk.farnell.com/fischer-elektronik/ick-s-14-x-14-x-10/led-heatsink-with-pins-square/dp/1850054). I've got a nice CPU fan left over from another project which fits my arty project well. However the fan is 12v. But I'm already powering the board with a external coaxial 5A 12v supply. Looking at the manual you ca
  9. icedefender

    Arty S7 step file

    I have found the step file for Arty board, but not for the Arty S7 board https://reference.digilentinc.com/reference/programmable-logic/arty-s7/start BTW the Arty borad looks great, I just need one for Arty S7 I would also like to get a 3d step file for "Pmod Clip: Mechanical Mount for Pmod boards" SKU: 240-107 https://store.digilentinc.com/pmod-clip-mechanical-mount-for-pmod-boards/
  10. Hello, I want to download Xilinx bit file from Raspberry Pi to Arty S7, and adept utility for ARM seems to be the solution for it. So, I tried the following steps and it almost seems to work except the last step. I used the same bit file with Adept System on Windows, so bit file seems to be fine, and I'm suspecting if the adept utility needs some kind of update for the database. I'm currently using digilent.adept.runtime_2.16.6-armhf.deb and digilent.adept.utilities_2.2.1-armhf.deb. Any advice will be appreciated. Thanks, Taehyun [email protected]:/home/arty# djtgcfg enum
  11. Hey everyone! I'm new to the forum (and fairly new to VHDL as well), and I was hoping you could help me with a problem. I have a project that I'm working on in Vivado (currently it's just some of the inner-workings of a CPU in development), and I'm trying to implement a container that helps me test the design on my FPGA board (Spartan 7 on a Digilent Arty-S7). The top-level module routes the clock input and reset button input on the FPGA in to the design (inverting the reset button input from active-low to active-high in the process), and routes a 4-bit vector out from the design to