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Found 18 results

  1. ozden.erdinc

    Microblaze DDR RAM

    Hello, I am using Arty7 board and I am strugglling with DDR3 RAM in Microblaze. I added to my design UART core Mig7 series core. Also, I have data set to write the DDR3 RAM after writing operation I will read these data set. Unfortunately, I couldnt upload into the DDR3 ram that data set. How can handle with thise issue? Can you help me?
  2. I am learning to use DMA in Scatter Gather mode. So i use example code ("xaxidma_example_sg_poll.c"). Using "xil_printf" function to see value, I am done with this but it only transmit 1 BD, and i want more. I edit "SendData" function like this to transmit 2 BDs. // i edit this code to transmit more than 1 BD static int SendPacket(XAxiDma * AxiDmaInstPtr) { XAxiDma_BdRing *TxRingPtr; u8 *TxPacket; u8 Value; XAxiDma_Bd *BdPtr; int Status; int Index; TxRingPtr = XAxiDma_GetTxRing(AxiDmaInstPtr); /* Create pattern in the packet to transmit */ TxPacket = (u8 *) Packet; Value = TEST_START_VALUE; for(Index = 0; Index < 2*MAX_PKT_LEN; Index ++) { TxPacket[Index] = Value; xil_printf ("TX addr: %x and value: %x\n\r", (unsigned int)(TxPacket+Index),(unsigned int)*(TxPacket+Index)); Value = (Value + 1) & 0xFF; } /* Allocate 2 BD */ Status = XAxiDma_BdRingAlloc(TxRingPtr, 2, &BdPtr); if (Status != XST_SUCCESS) { return XST_FAILURE; } for (Index = 0; Index < 2;Index ++){ /* Set up the BD using the information of the packet to transmit */ Status = XAxiDma_BdSetBufAddr(BdPtr, (UINTPTR) Packet); if (Status != XST_SUCCESS) { xil_printf("Tx set buffer addr %x on BD %x failed %d\r\n", (UINTPTR)Packet, (UINTPTR)BdPtr, Status); return XST_FAILURE; } Status = XAxiDma_BdSetLength(BdPtr, MAX_PKT_LEN, TxRingPtr->MaxTransferLen); if (Status != XST_SUCCESS) { xil_printf("Tx set length %d on BD %x failed %d\r\n", MAX_PKT_LEN, (UINTPTR)BdPtr, Status); return XST_FAILURE; } xil_printf ("TX BD addr: %x and value: %x\n\r", BdPtr,TxPacket); /* For single packet, both SOF and EOF are to be set */ XAxiDma_BdSetCtrl(BdPtr, XAXIDMA_BD_CTRL_TXEOF_MASK | XAXIDMA_BD_CTRL_TXSOF_MASK); XAxiDma_BdSetId(BdPtr, (UINTPTR)Packet); TxPacket += MAX_PKT_LEN; BdPtr = (XAxiDma_Bd *)XAxiDma_BdRingNext(TxRingPtr, BdPtr); } /* Give the BD to DMA to kick off the transmission. */ Status = XAxiDma_BdRingToHw(TxRingPtr, 2, BdPtr); if (Status != XST_SUCCESS) { xil_printf("to hw failed %d\r\n", Status); return XST_FAILURE; } return XST_SUCCESS; } And error appear from "XAxiDma_BdRingToHw()" function . Any suggestion for me ? Thank P.S: xaxidma_example_sg_poll.c : full code file I will post my project file soon.
  3. Regarding the the board Artix-7 (CMOD-A7) - https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual The datasheet says there is an 12 Mhz clock input and says the input clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. My question is, if I want an output clock signal to be 1 Mhz from this FPGA to some external hardware, would I have to do a clock computation (Convert 12Mhz to 1Mhz) in my verilog logic? Just want to clear that out, thanks.
  4. elevator program is not working on the board and it is showing simulation properly.i am not getting where the mistake is happend.can you check the program why it is not working on the board.i thought that the mistake is in the elevator module.it is not taking any inputs according to the module. thanks elevator12.txt
  5. How to connect the pins in the nexys4 artix7 temperature sensor
  6. 5v dc motor is not rotating when I connect to pmod ja0 and it is working fine when I connected to vcc and gnd in the pmod ja. anyone can help me .. ???
  7. Hi, I've a requirement to interface a CMOS Image sensor(MT9P006) with Artix7 FPGA. I've to perform image processing including autofocus and interfacing with USB 3.0 peripheral controller IC. Is it possible with artix7??? If yes, then what are the tools (like vivado ISE etc) required and what will be the expected cost for those tools... Is there any free software alternatives for them??? Thank you...
  8. Hello, I have a code that interface keyboard to display scan code. I have wireless keyboard that doesn't respond when I press key, while wire or old style keyboard work just fine. the keyboard model is logitech k400r
  9. Hello everybody, I am trying to send data from a Windows 10 computer to a Basys 3 board (Artix7 FPGA). I am using UART, and the data is entered via PuTTY, at 9600 bauds, with a stop bit and no parity. My VHDL module is based on a Finite State Machine (FSM), and two internal signals ensure the correct sampling (middle of the received bits). To test my VHDL module, I drive 8 LEDs on the board according to the received data. The problem : I manage to switch on / off the LEDs, but it doesn't seem to correspond to anyting (wrong ASCII code, or no difference between different key inputs...). So it seems I well receive data (TX lits on the Basys 3), but it is not processed correctly, and I cannot find why ! Could you please help me finding what's wrong ? ****** EDIT 1 *********************** I forgot to say that I tried to use another module found on the Internet ( https://www.nandland.com/vhdl/modules/module-uart-serial-port-rs232.html ), without any success (same issue). ******* END OF EDIT 1 ********** Please find hereafter my VHDL code & my .xdc : ## Clock signal set_property PACKAGE_PIN W5 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## LEDs set_property PACKAGE_PIN U16 [get_ports data_out[0]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[0]] set_property PACKAGE_PIN E19 [get_ports data_out[1]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[1]] set_property PACKAGE_PIN U19 [get_ports data_out[2]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[2]] set_property PACKAGE_PIN V19 [get_ports data_out[3]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[3]] set_property PACKAGE_PIN W18 [get_ports data_out[4]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[4]] set_property PACKAGE_PIN U15 [get_ports data_out[5]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[5]] set_property PACKAGE_PIN U14 [get_ports data_out[6]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[6]] set_property PACKAGE_PIN V14 [get_ports data_out[7]] set_property IOSTANDARD LVCMOS33 [get_ports data_out[7]] ##Buttons set_property PACKAGE_PIN T18 [get_ports RAZ] set_property IOSTANDARD LVCMOS33 [get_ports RAZ] ##USB-RS232 Interface set_property PACKAGE_PIN B18 [get_ports RxD_in] set_property IOSTANDARD LVCMOS33 [get_ports RxD_in] library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity UART_RX is Port ( RxD_in : in STD_LOGIC; clk : in STD_LOGIC; RAZ : in STD_LOGIC; data_out : out STD_LOGIC_VECTOR (7 downto 0)); end UART_RX; architecture Behavioral of UART_RX is signal tick_UART : STD_LOGIC; -- Signal "top" passage d'un état à l'autre selon vitesse connexion série signal double_tick_UART : STD_LOGIC; -- Signal précédent, fréquence * 2 signal compteur_tick_UART : integer range 0 to 10420; -- Compteur pour tick_UART signal double_compteur_tick_UART : integer range 0 to 5210; -- Compteur pour demi-périodes type state_type is (idle, start, demiStart, b0, b1, b2, b3, b4, b5, b6, b7); -- Etats de la FSM signal state :state_type := idle; -- Etat par défaut signal RAZ_tick_UART : STD_LOGIC; -- RAZ du signal tick_UART; signal RxD_temp : STD_LOGIC; -- RxD provisoire entre deux FF signal RxD_sync : STD_LOGIC; -- RxD synchronisé sur l'horloge begin D_flip_flop_1:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_temp <= RxD_in; end if; end process; D_flip_flop_2:process(clk) -- Clock crossing begin if clk = '1' and clk'event then RxD_sync <= RxD_temp; end if; end process; tickUART:process(clk, RAZ, state, RAZ_tick_UART) -- Compteur classique (tick_UART) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) or (RAZ_tick_UART = '1') then compteur_tick_UART <= 0; tick_UART <= '0'; elsif compteur_tick_UART = 10417 then tick_UART <= '1'; compteur_tick_UART <= 0; else compteur_tick_UART <= compteur_tick_UART + 1; tick_UART <= '0'; end if; end if; end process; doubleTickUART:process(clk, RAZ, state) -- Compteur demi-périodes (double_tick_UART car fréquence double) begin if clk = '1' and clk'event then if (RAZ='1') or (state = idle) then double_compteur_tick_UART <= 0; double_tick_UART <= '0'; elsif double_compteur_tick_UART = 5209 then double_tick_UART <= '1'; double_compteur_tick_UART <= 0; else double_compteur_tick_UART <= double_compteur_tick_UART + 1; double_tick_UART <= '0'; end if; end if; end process; fsm:process(clk, RAZ) -- Machine à état begin if (RAZ = '1') then state <= idle; data_out <= "00000000"; RAZ_tick_UART <= '1'; elsif clk = '1' and clk'event then case state is when idle => if RxD_sync = '0' then -- Si front descendant de RxD (= bit de start) et en idle state <= start; RAZ_tick_UART <= '1'; end if; when start =>if double_tick_UART = '1' then -- Demi période écoulée (pour échantillonage) state <= demiStart; RAZ_tick_UART <= '0'; -- Le compteur tick_UART commence à compter end if; data_out <= "00000000"; -- Reset des anciennes données when demiStart => if tick_UART = '1' then state <= b0; RAZ_tick_UART <= '0'; end if; data_out(0) <= RxD_sync; -- Acquisition bit 0 when b0 => if tick_UART = '1' then state <= b1; end if; data_out(1) <= RxD_sync; -- Acquisition bit 1 when b1 => if tick_UART = '1' then state <= b2; end if; data_out(2) <= RxD_sync; -- Acquisition bit 2 when b2 => if tick_UART = '1' then state <= b3; end if; data_out(3) <= RxD_sync; -- Acquisition bit 3 when b3 => if tick_UART = '1' then state <= b4; end if; data_out(4) <= RxD_sync; -- Acquisition bit 4 when b4 => if tick_UART = '1' then state <= b5; end if; data_out(5) <= RxD_sync; -- Acquisition bit 5 when b5 => if tick_UART = '1' then state <= b6; end if; data_out(6) <= RxD_sync; -- Acquisition bit 6 when b6 => if tick_UART = '1' then state <= b7; end if; data_out(7) <= RxD_sync; -- Acquisition bit 7 when b7 => if tick_UART = '1' then state <= idle; -- state <= stop; end if; end case; end if; end process; end Behavioral;
  10. Manas

    XADC demo

    Hi I have tried to execute the xadc demo code but keep getting the same error every time.Due to this error I'm unable to generate the bit file. Please help me solve this issue. Regards
  11. Hi, I'm trying to use xadc demo project to read sensor output and perform necessary action based on the xadc output. I'm getting the digital output when some analog signal is fed to the ports A18 and B18 of artix7. I'm stuck as how convert the values to ppm value so as to generate a warning system. Hope someone can help. Regards Manas
  12. I ran speech simulation (analog) on Matlab, and here is the code and result. I want create an analog stimulus file for UNISIM for XADC execution on Xilinx Vivado. I use Vivado 2015.4 with board Artix7 (xc7t35cpg236 - 1C). 1. How to make an analog stimulus file using these information? I will need Time(ns), VAUXP(V), TEMP, VCCINT, VCCAUX, VCCBRAM values. 2. How many set of readings can I take? 3. Should the time be in millisecond, nanoseconds or seconds? Please find attached 'SIM_MONITOR_FILE' saved in data.xls and the simulation file for word 'Jam', obtained using Matlab 'audiorecorder'. data.xls
  13. FPGAist

    Nexys4 Altium sources

    Hi, I would like to get the Altium schematics sources for the Nexys4 Artix7 board. Thanks!
  14. Hi, I'm trying to read the Configuration Flash of the Nexys4DDR. I need to achieve a relatively high speed. Here is a short summary of what I'm trying to do: My design will be controlled by an external master and there is no way to delay the masters request. The start address is latched first. After that I have about 1 us until the first read request will be applied. The subsequent reads will occur in a burst with a read cycle time of about 350 ns. Each read must deliver 16 bits of data to the master. I've been thinking about the QSPI-Flash as some kind of boot rom. And now I'm trying out if this is possible. With some combination of a high Frequency, the DDR and Quad I/O feature of the S25FL128S this could be done I believe. For the first step I got the SPI-Interface itself working using the Digilent SPI_If from the Nexys4DdrUserDemo. The SPI clock is output using the STARTUPE2. I could already read the device ID and some data successfully at 25 MHz. But at 50 MHz I'm reading garbage. Then I tested the maximum Configuration Rate (4 bit width) to find out if it is only a problem of my design. The Artix7 should be able to output a 100 MHz clock on the CCLK-Pin (FMCCK). The QSPI Flash should handle 133 MHz. But for me the maximum Configuration Rate is 40. Setting the CR to 50 will cause the FPGA to never load from SPI. Also when I attach my oscilloscope to the clock pin, the configuration at CR40 fails. So, my questions are: - What is (or should be) the maximum clock frequency of the Nexys4DDR QSPI design? - Is the FMCCK = 100 MHz only valid for configuration or is this also the maximum clock for the user design? - Do I have to constraint some attributes of the QSPI I/Os to achive a high clock? - Can this be done with "normal" logic or do I have to deal with something like SERDES? I'm using Vivado 2015.4 and have applied the contraints for "Clock signal" and "Quad SPI Flash" from the Nexys4DDR_Master.xdc from Digilent. Regards, Jago
  15. Hello all, Can anyone help me in Basys 3 project? I am trying to interface Analog Sensor to Basys3 XADC pin. I am trying to use the sample code given wiki basys3. Priority: 1) Where do we change in given code for any specific XADC pin. I could not find any 'pin' definition in behavior code. Why there are some IP code files there? It is not UART though. 2) How to generate PWM for Servo motor?
  16. Syaoran74

    Vmod+nexys 4

    Hi all, I am a 4th year engineering student from RMIT university of Australia. I'm in the search for FPGA board for the purpose of generating a depth map via stereo cameras, as part of a larger project. What has caught my eye is the Nexys4-DDR board primarily for its Xilinx Artix-7 chip and upon further searching the Digilent store i so found the VmodCAM module which may be particularly useful for the project. However i am aware as to the fact that the Nexys4 board does not have a VHDCI port and hence would like to know of any work arounds to this issue, possible PMOD cameras or other ways to connect a pair of cameras to the Nexys 4 board. Thank you for your time and assistance.
  17. This question was posted by Daedronus on the Nexys4DDR youtube video: Artix 7 can output directly hdmi video, why bother wasting IOs for the rather poor 12bit vga?
  18. ntallen

    Nexys4 Spi Flash

    In section 3 of the Nexys4 manual, it says: An Artix-7 100T configuration file requires just under four Mbytes of memory, leaving about 77% of the flash device available for user data. I spent some time trying to figure out how to accessthat available space but was thwarted by the fact that the configuration clock output at E9 is dedicated for use during FPGA configuration, so I can't drive it in my design to access the flash. Is there a work around for this that would actually make it possible to access this extra space?