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Found 8 results

  1. Hello, I have problem with board file for XC7A50T-2FGG484I in vivado 2015.4. I could not find anywhere board file to upload the vivado that family. Can you help me with this problem? Thank you.
  2. Sean Z

    Artix-7 FPGA Eval Bd.

    Hello, We are currently using the Xilinx XC7A100T Artix-7 FPGA and we are looking for some Evaluation board to study it. XC7A100T Artix-7 FPGA Evaluation Board 410-274: Nexys 4 DDR Artix-7 FPGA 410-292: Just wondering do we have Schematic .DSN files or layout files available? Thanks! Sean
  3. anurag

    ethernet with cmod A7

    hello, i want to know whether or not it is possible to connect ethernet port to CMOD A7. as number of input output lines are restricted .if yes then how?
  4. Hi, I'm new to this. I want to know how to describe in VHDL the operation of the ADC of the Nexys 4 to view it in LEDs. Any suggestion?
  5. Hi, I am trying to use microphone and audio-out of Nexys 4 board from Digilant. I have the following questions: 1. I implemented the refernce audio design provided by digilant which records audio for 5 seconds and play-back the recording from RAM. I noticed that both the interface namely micro-phone and audio-out operate on same clock domain and PDM interface. I tried to by-pass the RAM by directly connecting micro-phone output to audio-input (after 2 pipeline stages). But the design does not work as expected. Any thoughts on this will be appreciated. 2. I would also like to process the data received in FPGA via PDM. How do I convert this to N-bit digital signal of certain frequency which corresponding to the analog signal ? Should I do a moving average over certain terms. If so, how many terms? The figure 28 in the user-guide doesn't seem to be very clear. Thanks, Paul
  6. Hi, I am trying to use Vivado 2015.4's XADC in my design using Basys3 (xc7a35tcpg236-1). I do not know where to place my SIM_MONITOR_FILE (design.txt) so that the design reads it during simulation. Thank you, Shruthi
  7. A professor is going to switch from Spartan 3 to Nexys 4 DDR. He comes up the following problem. We’re still experiencing significantly longer synthesis/implementation times in ISE for Artix-7, compared to Spartan 3. I also tried the designs in Vivado, with similar results. This does depend a lot on the CPU in the computer running the software. My laptop (Intel Core i7) took 3:45 to do synthesis through place and route, whereas it took 9:26 in the lab and my desktop PC (Intel Core2 Quad Q8400). Add additional time for generating a configuration file. The Nexys4 sample project took over 13 minutes for implementation on my office PC. If there are any project options that you know of that would shorten this time, we would love to try them out. I have tried changing “Flow_RuntimeOptimize” to “Flow_Quick”, but for simple designs this only cut off a couple of seconds.
  8. I have done this project for an online class. The project is written by Verilog. The clock divider and counter modules were provided. My task was to write the top module to display 3 bit output of the counter on the 7 segment display. Originally, the project was implemented in Basys 2. I also used Xilinx ISE Webpack. Now, I modified the counter module and top module and implemented it on Basys 3. In addition, I used Vivado Webpack instead of ISE.