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Found 55 results

  1. I have done this project for an online class. The project is written by Verilog. The clock divider and counter modules were provided. My task was to write the top module to display 3 bit output of the counter on the 7 segment display. Originally, the project was implemented in Basys 2. I also used Xilinx ISE Webpack. Now, I modified the counter module and top module and implemented it on Basys 3. In addition, I used Vivado Webpack instead of ISE. http://m.instructables.com/id/How-to-use-Verilog-and-Basys-3-to-do-3-bit-binary-/
  2. Hi, I have a question about LEDs on the basys3 board. I'm using Verilog, and in my code I have a top level module which has other sub-modules within it. Like this: module top (); sub_module m1 (some_inputs, some_outputs); endmoduleIf I want to have the sub-module with an LED output, how would I go about doing it? I already tried having "output [15:0] led" in the definition of the top level module and also having it as an output of the sub level module, but that did not work. I also tried to simply declare led as a register within the sub_module, but that also didn't work.
  3. Hi, We have developed a nexys4 firmware for our pixel readout chip DAQ. We are using hardware TCP/UDP module (SiTcp) to communicate with board. You can find the project here: https://github.com/SiLab-Bonn/pyBAR/tree/development/firmware/nexys4 We extensively make use of basil framework: https://github.com/SiLab-Bonn/basil /Tomasz
  4. I am looking to familiarize myself with the Basys™2 Spartan-3E FPGA Board and would like to know which text would be most suitable. I am not familiar with VHDL or Verilog. I am interested in the text, "Digital Design" - 2nd edition. Any recommendations to get me started? Thank you!
  5. Hello, how can I implement this module using Verilog? And also, what is the meaning physical meaning of the 12 output bits of that module? Thanks in advance.