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Found 51 results

  1. hello, i am using cmod a7. i am trying to blink the led at 1 sec delay(using verilog language). please help me with the code and also let me know the frequency we will be using to create delay and at which pin will it be available.
  2. yassinema2018

    Zybo placing error

    i'm trying to make a pwm module that i want to use later with the sdk the module has two 32 bit inputs, the first is pwm up time and the second is pwmperiod the simulation is good but when i tried to implement the design, i had an placing error ( number of unplaced terminals is greater ....) as i understand vivado tries to give the two inputs a port with 64 bits my purpose is to assign a value to them from the sdk i tried declaring them as wires, integers, reg same error module pwm( input clk, input enable, output pwm_out, input [31:0] pwm_val, input [31:0] pwm_period ); the log file is attached , thank you implem_log.txt
  3. Hello This is the second project for me in FPGA for fun. I want to connect external board with 7 seg as a counter, so I put this Verilog code with this XDC file but the output is something error , could you please figure it out? I use common Anode display PMOD XADC pin 1 ---> pin 12 (7 Seg) pin 2 ----> Pin 9 pin 3 ---> Pin 8 pin 4 -----> pin 6 ------------------------ PMOD JB pin 1 ---> pin 11 pin 2----> pin 7 pin 3-----> pin 4 pin 4 ----> pin 2 pin 5 ----> pin 1 pin 6 ---> pin 10 pin 7 ----> pin 5 pin 8 ----> pin 3 Thanks seven.v Master_zybo.xdc
  4. So, I am starting to get these errors during the Place & Route phase WARNING:Par:288 - The signal kbd<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<3>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<4>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<5>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<6>_IBUF has no load. PAR will not attempt to route this signal. it only started when I added the enb register. It really makes no sense. `timescale 1ns / 1ps module Trigger(trig,trigb,kbd); output trig; output trigb; input[7:0] kbd; reg trigb; reg trig; reg enb; always begin trigb = kbd[7]; end always @* begin case(kbd) 0: begin enb = 0; trig = 0; end 254: begin // line 0 trig = 0; enb = 0; // kbdphase = 1; end 253: begin // line 1 trig = 0; enb =0; end 251: begin // line 2 trig = 0; enb =0; end 247: begin // line 3 trig = 0; enb =0; end 239: begin // line 4 trig = 0; enb =0; end 223: begin // line 5 trig = 0; enb =0; end 191: begin // line 6 trig = 0; enb = 1; end 127: begin // line 7 if (enb) begin trig = 1; enb = 0; end else begin enb = 0; trig = 0; end end default begin enb = 0; trig = 0; end endcase; end endmodule The idea behind this is that the C64's Keyboard has 8 Column lines that get strobed individually. The row lines will return the keys that are pressed on that column (not implemented). Right now it just throws a line (TRIG) when a line goes high. The problem is that the line 7 does not behave like exactly like the others. It can actually go low for other reasons but never after line 6. So I thought to put up an enable pin to be turned on during line 6 period and then this will let line 7 know it can do its job and it can set the enable register go low again. Anyways, the ISE is giving me a terrible time. Also I can't understand why it requires me to set the enb line low on practically every single part of the case statement... otherwise I get it complaining about a possible latch. Do you all notice anything I am doing wrong? Thanks a lot for any help you can provide.
  5. FlyMario

    FPGA Clock

    I am learning how to program a FPGA (spartan) lately. The language I am using is Verilog which is not really important to this question. I have the FPGA connected to my Commodore 64 via Logic Level Converters. And I am having lot of success. I am reading 8 lines from the Keyboard port looking. My verilog is simply looking for a matching value on those lines. No problems at all. But I am curious, how is the logic managing to work when I have not really set up a clocking line. Is the FPGA using main clock to trigger events to move on in the FPGA. For instance, if you have a blocking statement it would seem that in order to get past that block, there must be some clock checking the incoming value before the logic can continue. Is this true? Or am I missing something. Is there a clock in the fpga that is pushing the logic along? Flymario
  6. Hello to everyone, I'm getting the hex data in the processor and I want to print to pmod ssd. I have an incorrect number. How do I decode 8 bits of hex data? I am not good at English,sorry
  7. Hi. I have used combination of case and i-else statements. Now the problem is that first case executes successfully but second case never executes. While synthesizing on xilinx, it gives me an error saying that "case condition never applies". Does anybody know what is the problem? Thanks Saad
  8. I have the sample constraint file for my Arty board. I notice that where it says a clock signal is created in the file, it specifies a specific port that the clock is found on, specifically PACKAGE_PIN E3. set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}]; This creates a 100 MHz clock for the Arty. However, my current project needs a 20 MHz clock. I lack the FPGA knowledge to know whether these two lines of code are *describing* a clock that already exists at E3 on the Verilog board, or *creating* it. The "create clock" implies that it's creating, but the way the rest of the constraint file is formatted - with a list of the pins that exist on the Arty and their locations - suggests that it's only describing. Is it safe or even possible to make a 20 MHz clock by simply changing the number after -period to 50.00 for a 50 ns 20 MHz clock? Is there a way I can also keep the 100 MHz clock at the same time?
  9. how to implement 32 bit fma logic can be implemented on basys 3 kit.
  10. akshata@94

    simulation error

    hello guys, I am new to this forum . I am implementing md5 in Verilog. I am almost done with it somehow but still stuck half in a way.. can someone can help me in finding the bug in the rtl. I have referred pancham md5 source code for it and have modified a little bit as per my application. here, are the two attached files kindly help me in solving these issues. have been trying since long. I have to calculate the hash value of about 512 bytes but first of all trying from smaller input values md5.txt1.txt pancham_round.txt
  11. Hello. I'm new to Verilog and I was assigned to code a servo controller in Verilog. The system clock runs at 50MHz. The period of the servo is 20ms, the minimum pulse width is 0.6ms (at 0 degrees), at 1.5ms for 90 degrees, and 2.4ms for 180 degrees. When the user presses one of the buttons on the FPGA and the button corresponds to increment, the servo has to move 5 degrees clockwise. If the user presses the button corresponding to decrement, the servo has to move 5 degrees counterclockwise. Please help me. I looked online for resources but I don't seem to understand them. Thank you so much in advance!
  12. D@n

    Default nettype

    I recently came across this code piece, `default_nettype none I've never used it before, but several web sites and individuals I've personally talked with have recommended it to me as a way of avoiding those cases where Vivado does the wrong thing with my code. For example, I've had problems with Vivado doing strange things to my code when I don't pre-declare variables properly, problems that can be hard to find and track, and this little one-line change, added to a Verilog file should fix that. I intend to be trying this out soon, and I'd commend it to anyone who hasn't seen this before. Thought I'd share, Dan
  13. Hi, I tried to learn RS232 and created a project on Basys 3 with Pmod R232. The plan I would like to do is that whenever I set binary number at 8 switches on Basys 3, the data will be passed to the PC and I can see the character in the hyperterminal. At the same time, the LEDs for the "ON" switches with be turned on. I have successfully generated the bitstream file but it doesn't seems function. Include the Verilog code for transmitter, receiver and top modules. It will be great if someone can give hints to let me finish this project. P.S. I have used the logic from Transmitter module transmitter( input clk, //clock input reset, // reset input transmit, //input to say transmission is ready, can be push button or switch input [7:0] data, // data transmitted output reg TxD // transmit data line ); reg TxDready; //register variable to tell when transmission is ready reg [3:0] bitcounter; //vector 4 bits counter to count up to 9 reg [13:0] counter; //vector 14 bits counter to count the baud rate, counter = clock / baud rate reg state, nextstate; // register state variable reg [9:0] rightshiftreg; // vector data needed to be transmitted 1 start, 8 data & 1 stop bit reg shift, load, clear; //register variable for shifting, loading the bits and clear the counter //counter logic always @ (posedge clk) //positive edge begin if (reset) begin // reset is asserted (reset = 1) state <=0; // state is idle (state = 0) counter <=0; // counter for baud rate is reset to 0 bitcounter <=0; //counter for bit transmission is reset to 0 end else begin counter <= counter + 1; //start counting if (counter >= 10415) //if count to 5207 because we start the conunt from 0, so not 5208 begin state <= nextstate; //state change to next state counter <=0; // reset counter to 0 if (load) rightshiftreg <= {1'b1,data,1'b0}; //load the data if load is asserted if (clear) bitcounter <=0; // reset the bitcounter if clear is asserted if (shift) begin // if shift is asserted rightshiftreg <= rightshiftreg >> 1; //right shift the data as we transmit the data from lsb bitcounter <= bitcounter + 1; //count the bitcounter end end end end //state machine always @ (state, bitcounter, transmit,rightshiftreg) //trigger by change of state, bitcounter or transmit begin load <=0; // set load equal to 0 at the beginning shift <=0; // set shift equal to 0 at the beginning clear <=0; // set clear equal to 0 at the beginning TxDready <=1; // set TxDReady equal to 1 so no transmission. When TxD is zero, the receiver knows it is transmitting TxD <=0; // set TxD equals to 0 at the beginning to avoid latch case (state) 0: begin // idle state if (transmit) begin // assert transmit input nextstate <=1; // set nextstate register variable to 1 to transmit state load <=1; // set load to 1 to prepare to load the data shift <=0; // set shift to 0 so no shift ready yet clear <=0; // set clear to 0 to avoid clear any counter end else begin // if transmit not asserted nextstate <=0; // next state is 0 back to idle TxDready <=1; // set TxD to 1 to avoid any transmission end end 1: begin // transmit state if (bitcounter >=9) begin // check if transmission is complete or not. If complete nextstate <= 0; // set nextstate back to 0 to idle state clear <=1; // set clear to 1 to clear all counters end else begin // if transmisssion is not complete nextstate <= 1; // set nextstate to 1 to stay in transmit state shift <=1; // set shift to 1 to continue shifting the data TxD <= rightshiftreg[0]; // shift the bit to output TxD end end default: begin // idle state if (transmit) begin // assert transmit input nextstate <=1; // set nextstate register variable to 1 to transmit state load <=1; // set load to 1 to prepare to load the data shift <=0; // set shift to 0 so no shift ready yet clear <=0; // set clear to 0 to avoid clear any counter end else begin // if transmit not asserted nextstate <=0; // next state is 0 back to idle TxDready <=1; // set TxD to 1 to avoid any transmission end end endcase end endmodule Receiver module receiver( input clk, //input clock input reset, //input reset input RxD, //input receving data line output [7:0]RxData // output for 8 bits data // output [7:0]LED // output 8 LEDs ); reg shift; // register variable shift to trigger shifting data reg state, nextstate; // register state variable reg [3:0] bitcounter; // register vector 4 bits counter to count up to 9 reg [3:0] samplecounter; // register vector 4 bits sample counter to count up to 9 reg [13:0] counter; // register vector 14 bits counter to count the baud rate reg [9:0] rxshiftreg; //register vector for bit shifting reg clear_bitcounter,inc_bitcounter,inc_samplecounter,clear_samplecounter; //register variable to clear or increment the counter assign RxData = rxshiftreg [8:1]; // assign the RxData // assign LED = RxData; // assign the LED output //counter logic always @ (posedge clk) begin if (reset)begin // if reset is asserted state <=0; // set state to idle bitcounter <=0; // reset the bit counter counter <=0; // reset the counter samplecounter <=0; // reset the sample counter end else begin // if reset is not asserted counter <= counter +1; // start count in the counter if (counter >= 3472) begin // if counter reach the baud rate with sampling counter <=0; //reset the counter state <= nextstate; // assign the state to nextstate if (shift)rxshiftreg <= {RxD,rxshiftreg[9:1]}; //if shift asserted, load the receiving data if (clear_samplecounter) samplecounter <=0; // if clear sampl counter asserted, reset sample counter if (inc_samplecounter) samplecounter <= samplecounter +1; //if increment counter asserted, start sample count if (clear_bitcounter) bitcounter <=0; // if clear bit counter asserted, reset bit counter if (inc_bitcounter)bitcounter <= bitcounter +1; // if increment bit counter asserted, start count bit counter end end end //state machine always @ (state or RxD or bitcounter or samplecounter or rxshiftreg) // triggered by change of state, Rxd and bit counter begin shift <= 0; // set shift to 0 to avoid any shifting clear_samplecounter <=0; // set clear sample counter to 0 to avoid reset inc_samplecounter <=0; // set increment sample counter to 0 to avoid any increment clear_bitcounter <=0; // set clear bit counter to 0 to avoid claring inc_bitcounter <=0; // set increment bit counter to avoid any count nextstate <=0; // set nextstate equals to 0 at the beginning to avoid any latch case (state) 0: begin // idle state if (RxD) // if input RxD data line asserted nextstate <=0; // back to idle state because RxD needs to be low to start transmission else begin // if input RxD data line is not asserted nextstate <=1; //jump to receiving state clear_bitcounter <=1; // trigger to clear bit counter clear_samplecounter <=1; // trigger to clear sample counter end end 1: begin // receiving state if (samplecounter==1) shift <=1; // if sample counter is 1, trigger shift if (samplecounter==3) begin // if sample counter is 3 as the sample rate used is 3 if (bitcounter ==9) begin // check if bit counter if 9 or not nextstate <= 0; // back to idle state if bit counter is 9 as receving is complete end inc_bitcounter <=1; // trigger the increment bit counter if bit counter is not 9 clear_samplecounter <=1; //trigger the sample counter to reset the sample counter end else inc_samplecounter <=1; // if sample is not equal to 3, keep counting end default: begin // idle state if (RxD) // if input RxD data line asserted nextstate <=0; // back to idle state because RxD needs to be low to start transmission else begin // if input RxD data line is not asserted nextstate <=1; //jump to receiving state clear_bitcounter <=1; // trigger to clear bit counter clear_samplecounter <=1; // trigger to clear sample counter end end endcase end endmodule Top module top( input btn0, input [8:0] sw, // input 8 switches , one for transmit input clk, input RxD, output TxD, output [7:0]LED // output 8 LEDs ); wire [7:0] data; assign data = sw; receiver R1 (.clk(clk), .reset(btn0), .RxD(RxD), .RxData(LED)); transmitter T1 (.clk(clk),.transmit(sw[8]), .reset(btn0),.data(sw[7:0]), .TxD(TxD)); endmodule
  14. sidies95

    Basys3 Bluetooth

    Hi guys, I really need to connect basys3 with bluetooth. However, I have no idea how to do that. Please help me
  15. Hi, I have problems with my counter. Sorry for my poor english Register should be reset on the posedge of signal x1 and should be increased on the posedge of CLOCK. I know that register can be changed only in one always process, but I don't know how do that. The error is: Line 33: Signal register[11] in unit blagam_o_synteze is connected to following multiple drivers: blagam_o_synteze.v
  16. How to send data from pc to nexys4 through ethernet, kindly guide me how to configure the ethernet protocol in nexys4. Urgent help required.
  17. Hello all, I'm trying to use XADC aux channel-6 outputs as input to my unit under test. The CFBLMS module has input parameters for every change in the MEASURED_AUX6 voltage. Can you help me how to do that? Below is the code, and bolded is the part where I wish to take every change in the value of MEASURED_AUX6 as a separate input parameter. `timescale 1ns/1ps module ug480_tb; reg [3:0] VAUXP, VAUXN; reg VP, VN; reg RESET; reg DCLK; wire [15:0] MEASURED_TEMP, MEASURED_VCCINT, MEASURED_VCCAUX; wire [15:0] MEASURED_VCCBRAM, MEASURED_AUX6, MEASURED_AUX7; wire [15:0] MEASURED_AUX14, MEASURED_AUX15; wire [7:0] ALM; wire OT; wire EOC; wire EOS; wire [4:0] CHANNEL; initial begin DCLK = 0; RESET = 0; end always #(10) DCLK= ~DCLK; // Instantiate the Unit Under Test (UUT) ug480 uut ( .VAUXP (VAUXP), .VAUXN (VAUXN), .RESET (RESET), .ALM (ALM), .DCLK (DCLK), .MEASURED_TEMP (MEASURED_TEMP), .MEASURED_VCCINT (MEASURED_VCCINT), .MEASURED_VCCAUX (MEASURED_VCCAUX), .MEASURED_VCCBRAM (MEASURED_VCCBRAM), .MEASURED_AUX6 (MEASURED_AUX6), .MEASURED_AUX7 (MEASURED_AUX7), .MEASURED_AUX14 (MEASURED_AUX14), .MEASURED_AUX15 (MEASURED_AUX15) ); integer i [0:4]; wire [15:0] e [0:3] reg [15:0] x [0:3]; initial begin for (i=0; i<4; i=i+1) begin x = MEASURED_AUX6; end end CFBLMS uut (.x_00(x[0]), .x_01(x[1]), .x_02(x[2]), .x_03(x[3]), .e0(e[0]), .e1(e[1]), .e2(e[2]), .e3(e[3])); endmodule Thank you, Shruthi Sampathkumar.
  18. Hello all, I'm trying to simulate LMS algorithm with digital samples from XADC out of Auxillary channel 6. In my step to update weight, I don't understand how to bring about weight update. It reads Weight_in and Weight_out as XXXX. Please check the bolded. area in LMS_weight module. *********************** module LMShruthi ( DCLK, RESET, Desired_in, mux ); input DCLK, RESET; input signed [15:0] Desired_in; output signed [15:0] mux; wire [15:0] mu; //mu=0.0000001 reg signed [15:0] Data_in; wire signed [15:0] e; wire signed [31:0] Product_32, y; assign mu = 16'b0000000001100110; always # (50000) Data_in = Desired_in; assign Product_32 = mu * Data_in; assign mux = Product_32[24:9]; LMS_weight uut3 ( .DCLK(DCLK), .RESET(RESET), .Data_in(Data_in), .mux(mux), .y(y) ); assign e = Desired_in - y[24:9]; endmodule *********************************************************** module LMS_weight (DCLK, RESET, Data_in, mux, y); input DCLK,RESET; input signed [15:0] Data_in,mux; output signed [31:0] y; wire signed [15:0] Weight_in; wire signed [15:0] Weight_out, emux; wire signed [31:0] Product_32; assign Product_32 = Data_in * mux; assign emux = Product_32[26:11]; assign Weight_in = (RESET==1'b1) ? 16'h0000 : (emux + Weight_out); assign y = Weight_out * Data_in; endmodule *********************************************************** Thank you, Shruthi Sampathkumar.
  19. laltarac

    Basys2 PS/2 Keyboard

    Hello. Im working on a project that requires a ps2 keyboard to communicate to the Basys2 board. Does any one have any good links that might help me get started with this. Or, maybe would someone be able to post their Verilog code , if they've done it ? It would be much appreciated Thanks Liam
  20. I realize I only know a tiny corner of all of VHDL. I know little about creating packages, libraries, other data types outside of 'std_logic' and 'signed', 'unsigned', 'integer' and 'natural', things like "a <= b after 10 ns;", string handling, file handling, structures, text I/O ..... the list goes on and on. Just how much of VHDL do you need to work with FPGAs? My guess is about 20% And once you get that far, is it worth learning more? And is Verilog the same? And does anybody have any recommended resources on more advanced VHDL?
  21. I have done this project for an online class. The project is written by Verilog. The clock divider and counter modules were provided. My task was to write the top module to display 3 bit output of the counter on the 7 segment display. Originally, the project was implemented in Basys 2. I also used Xilinx ISE Webpack. Now, I modified the counter module and top module and implemented it on Basys 3. In addition, I used Vivado Webpack instead of ISE.
  22. Hi, I have a question about LEDs on the basys3 board. I'm using Verilog, and in my code I have a top level module which has other sub-modules within it. Like this: module top (); sub_module m1 (some_inputs, some_outputs); endmoduleIf I want to have the sub-module with an LED output, how would I go about doing it? I already tried having "output [15:0] led" in the definition of the top level module and also having it as an output of the sub level module, but that did not work. I also tried to simply declare led as a register within the sub_module, but that also didn't work.
  23. Hi, We have developed a nexys4 firmware for our pixel readout chip DAQ. We are using hardware TCP/UDP module (SiTcp) to communicate with board. You can find the project here: We extensively make use of basil framework: /Tomasz
  24. I am looking to familiarize myself with the Basys™2 Spartan-3E FPGA Board and would like to know which text would be most suitable. I am not familiar with VHDL or Verilog. I am interested in the text, "Digital Design" - 2nd edition. Any recommendations to get me started? Thank you!