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  1. I have a PmodOLED display board connected to the JA header on an ARTY board by Digilent. I am using Verilog and have tried version 16.4 and 17.1. I am using the supplied sample code to write to the display for the first time. When I try to "Program Device" I get the following error message: [Labtools 27-3303] Incorrect bitstream assigned to device. Bitfile is incompatible for this device. Can someone please tell me what the problem may be? Thanks, Dave
  2. tekson


    Hi all, How to implent delay in verilog code? I want to run a led blink code with one second delay using zynq zybo-7-z10 Thanks in advance
  3. I am trying to implement Decimation on FPGA and Matlab For this task i chose following design parameters Filter type=window hamming hamming method filter order=30 decimation factor=10 input sample rate=2Ms/s output sample rate=200ks/s Normalized cuttof =1/decimation factor First i implement it on MATLAB and use this sequence Filter handle filter delay downsample Using above sequence i successfuly implement it on MATLAB For FPGA i use fir compiler core in which i paste the same coefficients that is generated through matlab But the problem i face is fir
  4. I'm trying to get the picosoc project working on a CMOD A7. This is a soft-CPU running code directly from an SPI flash chip, hence I want to get access to the N25Q032A13EF440F pins from verilog. Looking at the Schematic and the .xdc file from the board support package, I can find definitions for qspi_cs and qspi_dq[0-4], which are the chip select and data lines respectively. However there is no definition for for the QSPI_SCK net, which connects to the FPGA pins CCLK_0 and IO_L3N_T0_DQS_EMCCLK_14, both of which are not defined in the .xdc file. Is that deliberately so? Cheers
  5. Hi all, A new website is offering FPGA projects and ZYNQ step by step tutorials with full source codes, maybe it is useful :
  6. Hello everyone, I'm using Zybo and i want to create a custom ip. The ip will have two inputs (as registers) that has 32 bits: Let's call them a[31:0] and b[31:0]. And i want to get memory value at a and add b. The calculated value is a new memory address and i want to read value at that address and write it into the third register of ip. But i haven't find a tutorial like this. If there's any, i would like to know it. Thanks for your time.
  7. Hello, I am using xilinx spartan 6 sp6-x9 board in which its led's and switch works on active low logic. Is it possible to convert switch and leds to to active high logic
  8. Once again I'm sorry if I'm asking what can be considered silly questions, but I'm diving into the FPGA world by myself and I'm having serious dificulties finding documentation or examples that fit my questions. I'm using a Cmod A7 and I want to develop a GUI to let the user define some parameters. Through what I've been researching I believe the way to do it is using UART with the micro usb of the board. I've seen some examples of UART implementations, some I found in responses here on the forum, but due to my lack of knowledge it seems to me they lack important things so I could underst
  9. hello, i am using cmod a7. i am trying to blink the led at 1 sec delay(using verilog language). please help me with the code and also let me know the frequency we will be using to create delay and at which pin will it be available.
  10. i'm trying to make a pwm module that i want to use later with the sdk the module has two 32 bit inputs, the first is pwm up time and the second is pwmperiod the simulation is good but when i tried to implement the design, i had an placing error ( number of unplaced terminals is greater ....) as i understand vivado tries to give the two inputs a port with 64 bits my purpose is to assign a value to them from the sdk i tried declaring them as wires, integers, reg same error module pwm( input clk, input enable, output pwm_out, input [31:0]
  11. Hello This is the second project for me in FPGA for fun. I want to connect external board with 7 seg as a counter, so I put this Verilog code with this XDC file but the output is something error , could you please figure it out? I use common Anode display PMOD XADC pin 1 ---> pin 12 (7 Seg) pin 2 ----> Pin 9 pin 3 ---> Pin 8 pin 4 -----> pin 6 ------------------------ PMOD JB pin 1 ---> pin 11 pin 2----> pin 7 pin 3-----> pin 4 pin 4 ----> pin 2 pin 5 ----> pin 1 pin 6 ---> pin 10
  12. So, I am starting to get these errors during the Place & Route phase WARNING:Par:288 - The signal kbd<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<3>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<4>_IBUF has no load. PAR will not attempt to route this si
  13. FlyMario

    FPGA Clock

    I am learning how to program a FPGA (spartan) lately. The language I am using is Verilog which is not really important to this question. I have the FPGA connected to my Commodore 64 via Logic Level Converters. And I am having lot of success. I am reading 8 lines from the Keyboard port looking. My verilog is simply looking for a matching value on those lines. No problems at all. But I am curious, how is the logic managing to work when I have not really set up a clocking line. Is the FPGA using main clock to trigger events to move on in the FPGA. For instance, if you have a blo
  14. Hello to everyone, I'm getting the hex data in the processor and I want to print to pmod ssd. I have an incorrect number. How do I decode 8 bits of hex data? I am not good at English,sorry
  15. Hi. I have used combination of case and i-else statements. Now the problem is that first case executes successfully but second case never executes. While synthesizing on xilinx, it gives me an error saying that "case condition never applies". Does anybody know what is the problem? Thanks Saad
  16. I have the sample constraint file for my Arty board. I notice that where it says a clock signal is created in the file, it specifies a specific port that the clock is found on, specifically PACKAGE_PIN E3. set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}]; This creates a 100 MHz clock for the Arty. However, my current project needs a 20 MHz clock. I lack the FPGA knowledge to know whether these two lines of code are
  17. how to implement 32 bit fma logic can be implemented on basys 3 kit.
  18. hello guys, I am new to this forum . I am implementing md5 in Verilog. I am almost done with it somehow but still stuck half in a way.. can someone can help me in finding the bug in the rtl. I have referred pancham md5 source code for it and have modified a little bit as per my application. here, are the two attached files kindly help me in solving these issues. have been trying since long. I have to calculate the hash value of about 512 bytes but first of all trying from smaller input values md5.txt1.txt pancham_round.txt
  19. Hello. I'm new to Verilog and I was assigned to code a servo controller in Verilog. The system clock runs at 50MHz. The period of the servo is 20ms, the minimum pulse width is 0.6ms (at 0 degrees), at 1.5ms for 90 degrees, and 2.4ms for 180 degrees. When the user presses one of the buttons on the FPGA and the button corresponds to increment, the servo has to move 5 degrees clockwise. If the user presses the button corresponding to decrement, the servo has to move 5 degrees counterclockwise. Please help me. I looked online for resources but I don't seem to understand them. Thank you so much
  20. I recently came across this code piece, `default_nettype none I've never used it before, but several web sites and individuals I've personally talked with have recommended it to me as a way of avoiding those cases where Vivado does the wrong thing with my code. For example, I've had problems with Vivado doing strange things to my code when I don't pre-declare variables properly, problems that can be hard to find and track, and this little one-line change, added to a Verilog file should fix that. I intend to be trying this out soon, and I'd commend it to anyone who hasn't seen thi
  21. Hi, I tried to learn RS232 and created a project on Basys 3 with Pmod R232. The plan I would like to do is that whenever I set binary number at 8 switches on Basys 3, the data will be passed to the PC and I can see the character in the hyperterminal. At the same time, the LEDs for the "ON" switches with be turned on. I have successfully generated the bitstream file but it doesn't seems function. Include the Verilog code for transmitter, receiver and top modules. It will be great if someone can give hints to let me finish this project. P.S. I have used the logic from Tr
  22. sidies95

    Basys3 Bluetooth

    Hi guys, I really need to connect basys3 with bluetooth. However, I have no idea how to do that. Please help me
  23. Hi, I have problems with my counter. Sorry for my poor english Register should be reset on the posedge of signal x1 and should be increased on the posedge of CLOCK. I know that register can be changed only in one always process, but I don't know how do that. The error is: Line 33: Signal register[11] in unit blagam_o_synteze is connected to following multiple drivers: blagam_o_synteze.v
  24. How to send data from pc to nexys4 through ethernet, kindly guide me how to configure the ethernet protocol in nexys4. Urgent help required.