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Found 180 results

  1. muse

    PmodOLEDrgb with Basys 3

    Hello I have a project which involves getting an image displayed on PmodOLEDrgb. I use Basys 3 Board under Vivado 2016.2. I've used the tutorial from At step 5, it is said to add ZYNQ7 Processing System to my design. Since I am using a board different from Zybo, what should I add to the system? One more thing, I followed all the steps , but at step 8 when I click File>Launch SDK I get Application Exception: Not found in path: xsdk error. What can be causing this? Any help would be highly appreciated! Thanks!
  2. Hello, I am designing an extension board that needs to use two pmods at the same time. Does anyone know the distance between two pmods on the long side of the ZYBO? I can measure them later today, but I thought it would be better to get an exact answer if possible.
  3. Is it possible to use PMOD devices with the Beaglebone Black board?
  4. PALM

    PMOD AD1 on Nexys4

    Hi, I recently purchased a nexys 4 board and a Pmod AD1 to get short latency audio input to the fpga. Is there any vhdl example available to get audio samples from the AD1? the Digilent ressource center does not have any ... thanks, Pierre
  5. k_hades1

    Pmod compability

    I've a DE0 Nano board and I wonder if Digilent Pmod modules are compatible with my board. Thanks
  6. Hello. I need to use two Pmod on ZedBoard. I already know how to communicate with one Pmod, by building a Vivado project with a Quad SPI IP in the block design, and than pin assigning it to a Pmod connector on the board. Should I use two of such IPs? I tried but I think what I did is wrong, since no connector is "active". Thank you.
  7. I'm having problems with IOSTANDARD specifications on the PMOD ports of the ZYBO. My design utilizes most of the PMOD ports, namely JB-JE, and on one of the ports I want to output a 2.5V LVCMOS signal (named "Sync"). The other signals are all 3.3V LVCMOS. Trying to implement this on the ZYBO yeilds the following message: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (1) is greater than number of available sites (0). The following Groups of I/O terminals have not sufficient capacity: IO Group: 1 with : SioStd: LVCMOS25 VCCO = 2.5 Termination: 0 TermDir: Out RangeId: 1 Drv: 16 has only 0 sites available on device, but needs 1 sites. Term: Sync Attached is an example of my .XDC file. It's a bit messy since it was created manually first, then edited with the I/O Ports window. I'm wondering if it's possible to do what I'm asking. From my research, it sounds like there aren't enough I/O Banks to support so many outputs, with one output requiring a different VCCO. Is this accurate? iostandard_problem.xdc
  8. Hi all, I'm looking to use Digilent's Ambient Light Sensor as an add-on for a project I'm doing. I can't use the example code given because I'm using a little bit more complex of a coding environment (Eclipse). I've managed to translate so to speak most of the example code to work for my environment, but one thing I'm struggling with is creating the correct initialization code in my environment. Does anyone have any experience coding the ALS outside of an Arduino-like environment or can tell me what I need to do to initialize it correctly? Thanks!
  9. Kindly I need to know the difference between host and peripheral in the Pmod interfaces. Thanks
  10. Hi, I am using a Xilinx ZC706 development board and I would like to connect pmod modules to it. However, the ZC706 development board has dual row header pins for the pmod interface and it seems that all of the pmod modules have header pins for the interface too. What is the best way to interface the pmod modules with header pins to the ZC706 dev board that has header pins for the pmod interface too? Thanks!
  11. I cannot, for the life of me, get this: work. I'm fairly confident I have the clocks at the correct frequencies. And I've tried sending a square wave at about 12kHz ranging from max amplitude: 0111111111111111 to min amplitude: 1000000000000000 (2's compliment). But when I plug in my headphones, I do not hear anything... Does this thing need an amplifier? Any help would be greatly appreciated!
  12. Hi , I am trying to make an adapter board for ZYBO. The adapter board is used to interface a camera sensor module to the Pmod connector. Can anyone help me to get the PCB layout and Mechanical details for the ZYBO board.? Thanks in advance,
  13. I'm really new to this all, so apologies. I couldn't find a simple answer to my question about the PMOD connectors (specifically the standard PMOD JE) on the ZYBO. I have, for example, an 8 bit counter in VHDL. I want to output these 8 bits to JE. It's all very simple, but I'm not sure how to start. I've read tutorials which go far more complex than I want to right now. I've tried creating an IP block out of VHDL code, and I've also tried just adding the "Binary Counter" IP block. 1. How do I get a clock signal to input to the counter? I tried adding an IP called "Clocking Wizard," and running the Connection Automation. Then I get errors about being unable to place reset_rtl, which was an input created by the Connection Automation. 2. Is there a tutorial that I've missed somewhere, which outlines creating a simple design and outputting something on the PMOD pins?
  14. hi! Does anyone know if I can use my usb to uart pmod, which is connected to a zedboard, to communicate with a device as a host? I want the zedboard to be the host of the communication and send specific data packets to the attached device. I test the pmod with a usb analyzer and see that it works as a device(slave). Can I make it a host(master) or it sends by default specific data header? And if yes how this can be ? I’m really new on embedded design and I really need some help… Thanks in advance!
  15. Hello, I have combed through the forums but still have not found the answer I am looking for. I have the Arty board and Vivado 2015.4. I can create a project and I can select the Arty board in that process. I create a Block diagram on which to start building my 'circuit'. At this point I try two different ways to get a pmod port on the board: I click on the 'Board' tab and I find all the input and output ports (led, led_rgb, buttons, switches, spi, etc and Connector JA thu JD). I try and bring a JA onto the block diagram and get a message "Conn JA board component cannot be connected because no possible options to connect". Second thing I try is to click on 'Add IP' and select AXI_GPIO. Double click that and have the option to re-customize this block. Under 'Board Interface' is a drop down menu with , again, all the input/output items on the Arty board, but no pmod ports. I have tried this with and without bringing in the latest constraints file (from Github) with the same negative results. What does it take to get the pmod ports (Connectors JA-JD) on the block diagram? Switches and buttons and leds do move to the Block Diagram and they create an AXI block when they do. So what am I missing? Thank you for your time and help.
  16. I need to use 10 PModAD1 (1x6) on Zedboard where there are only 5 Pmod(2x6). I wonder whether I can plug in 2 PModAD1 in the same Pmod on Zedboard. What I concern most is not the hardware compability but the sofware compability, that is to say whethter it is possible to use dirctly the library of Pmod in the IDE FPGA after this modification. Dose anyone have experience for this question? Your suggestion will be greatly appreciated.
  17. I trying to use the PmodI2S for the first time, but am unable to get sound from the port. I read thru the post "Pmodi2s Stereo Output Pmod - How Can I Get This Thing To Work?", but unfortunately it didn't solve my issue. I'm sending I2S audio to the pmodI2S module with a PIC32. The PIC32 is toggling the MCLK pin at 8.3 MHz (I've also tried 11 MHz). Here are the frequencies on the pins, verified with a scope: - MCLK (pin 1): 8.3 MHz (Supplied by PIC32) - LRCK (pin 2): ~31.45 kHz (2x channels) - SCK (pin 3): 2 MHz (I've tried it with the PIC32 supplying this and without supplying it, i.e. internal. When relying on internal, it outputs nothing.) - SDIN (pin 4): 16-bit data, 32-bits per channel (2x channels) = 64-bit frames - GND (pin 5): GND - VCC (pin 6): 3.3v I'm using Apple headphones that came with my phone to connect to the output jack. Been fighting this one for many several hours. Any help will the greatly appreciated. Thanks
  18. We've gotten the second SD controller working on Zedboard and Zybo, using PMOD SD connected via either the MIO PMOD E connector or EMIO and one of the other PMOD connectors. We've tested it with SD cards and with an Atheros WiFi card. There are a number of changes to make in order to get it working. 1) Configure MIO to connect the second controller to the MIO pins. Or Configure MIO so that the second controller is connected to none of the MIO pins so that it can be connected via EMIO and programmable logic. We did this in clearreg.c, which is run by our FSBL before it jumps to the entry point of zImage. 2) If attaching the SD card slot to MIO, use fly wires to swizzle the signals onto the right pins. If using EMIO, add the connection of the appropriate pins to the SD controller in the programmable logic. 3) The controller cannot run at full speed with fly wires or our EMIO logic, so added code to reduce the clock frequency used by the controller. 4) We program the logic after booting Linux, so we added a second SD devuce driver that we could load as a module after we programmed the logic. It reads the configuration from DTS just like the xilinx one. It would be nice to have a PMOD SD whose pinout matches Zedboard and Zybo so that MIO could be used without fly wires. It would be much tidier and would run faster.
  19. As I work with the chipKIT WF32 and the WiFIre, I find that making external connections to these processor boards is not as convenient as they are for the chipKIT Pro MX7 that has Pmod connectors JA through JF. Additionally there are limited pins for taking 3.3V/5V and ground off board. I can only assume that these chipKIT boards were always intended to be used with a shield of some sort. If Digilent makes IO shields specifically for the WF32 and WiFire, please advise. Meanwhile, I find the the Pmod Shield-Uno can be used to provide standard Pmod connections provided a few modifications are made. 1. The bottom side female connectors for JP6-JP8 must be removed because the USB connector J13 on the Wf32 and WiFire are in the way. This is easily done by gently bending the female connectors on the bottom of the Shield-Uno back and forth until they break off at the surface of the PCB. The schematic diagram for the Pmod-Shield does not show a connection for the center pin of JP6 and JP8. Can I assume that since JP6 and JP8 do not feed through to the WF32 or the WiFire that A04/A18 and A05/A19 are not functional? 2. I observed that pins 1 and 2 of J3 on the WF32 / WiFire have no connection to J5 on the Pmod-SHield. This appears not to be an issue since J3:1 is not connected and J3:2 has jumper to J3:4. 3 J6 of the WF32 / WiFire has no connection to the Pmod-Shield making connections to I2C2 unavailable. I could not find a secondary connection for SCL2 and SDA2. 4. Although the majority of the processor programming is done in the Arduino IDE environment using the serial port, there are times that debugging with the MPLAB X IDE is beneficial. Hence, I permanently soldered a single row right angle 6 pin header in JP2. This allows me to slip on and off a chipKIT programmer without removing the shield. Do you for see any problems such as RFI emissions? 5. Reading through the Pmod Shield-Uno users manual I see that the signal names for JA and JB are the same. The chipKIT pin numbers appear to be correct. Digilent should update the users manual.
  20. Hi! My professor loaned to me their Digilent BASYS2 FPGA board. We wish to develop an FPGA-based Laser Remote Sensor (LIDAR) system. The BASYS2 will be triggered by the pulse driver of our Laser Diode. The Laser Diode pulses will be detected by a photomultiplier tube detector at selected rates and bin widths. We will connect the output (analog) of the photomultiplier tube to the BASYS2. How can we do this? Is it via the PMOD? Do we need an A/D converter like the PMOD AD1 or PMOD AD2? The BASYS2 has 4 PMODs with 6 pins each. Which PMOD (AD1 or AD2) is better for us? The AD1 has 6 pins only but has 2 channels while the AD2 has 12 pins and 4 channels (and is also half the price). If we buy the AD2, can we connect it to two PMODs in the BASYS2? Will this work? For another question, once the BASYS2 receives a trigger, the BASYS2 will read the PMOD to get the analog reading from the photomultiplier tube. How can we get the reading? Is it via the register address for that PMOD? Since this is digital, how can we know the voltage reading of the photomultiplier tube? Sorry for asking too many questions. Thanks in advance! Sincerely, Edgar Vallar
  21. ANorman

    ESD protection on Pmod

    What is the P/N of TVS protection diodes D1-D10 on Zybo Board? If the PN is a proprietary info, what is the ESD protection voltage for those diodes?
  22. Hi all, I've recently bought an Arty board (Microblaze processor) and some Pmods (PmodDPOT, PmodDAs, PmodADs), which use SPI protocol. I've looked everywhere for an example on how to access the Pmod headers or just how to use Pmods with the Arty but I couldn't find anything (even on the reference wiki page for the Arty). I found a library for SPI on Xilinx SDK which is called Xspi but I also am not sure how to use it. Can anybody perhaps help me by giving me the basic steps on how to do this? I'm very new to FPGA, so any feedback or suggestions are welcome! Thanks Viv
  23. Greetings all! I've been trying on and off since September to get a simple sawtooth to sound from the PMODAMP3, so that I can eventually make music with it. Here are my intended settings: JP5 unloaded: Standalone mode JP6 unloaded: 0dB gain JP3 loaded: i2s format JP4 loaded: MCLK = 256*fs JP2 loaded BCLK side. BCLK = fs*64 = MCLK/4 = 2.5MHz, therefore MCLK = 10MHz, fs = 39kHz I've attached the code in 4 Verilog files: Basys3_Abacus_Top.v (name inherited from example project), sclk_div.v (generates BCLK from FPGA clk), i2s_tx.v (i2s transmitter), and oscillator.v (produces a simple 1Hz sawtooth), as well as test benches for i2s_tx and Basys3_Abacus_top. All of these files are relatively simple. In addition, I've attached the constraint file, and an image of the output, taken with my DSO NANO V3. Furthermore, I've zipped up the entire project and uploaded here: Some thoughts: Maybe SSM2518 doesn't know to generate MCLK as 4xBCLK? Faulty chip? Anyways, if one of you has the time and energy to either point out flaws in my verilog or hardware setup, I would be very grateful. TIA oscillator.v i2s_tx.v sclk_div.v i2stx_tb.v Basys3_Master.xdc Basys3_Abacus_Top.v IMG_001.BMP
  24. Hello Community, tried the library PMODOLED adapt, so that I can use from my Cerebot Pro MX7 at port JE. Unfortunately, however, comes only noise from the display. Has anyone any idea what I have done wrong? thank all inputs main.c PmodOLED.c PmodOLED.h
  25. Hello, I am new to this forum, so I may introduce myself first. I am from Germany and currentlly visiting a technical college here. Next year I will go to a University to study electronic engineering. My biggest hobby is to waste some time with electronics. I really like microcontroller and spend already some time programming them. Now I want to continue with FPGAs. I want to be able to handle some faster data transmissions compared to microcontrollers. My questions now are about the Pmod connectors. How fast data transmissions can I get? In the document which is aviable at the Zybo page there is written that a regular pin can handle 24MHz. How about the high-speed Pmods? Will it be able to achive a maximum of about 200MHz? Is it possible to short the 200Ohm resistors of the normal Pmods to use them as high-speed Pmods or is the PCB layout not suitable? Greetings, MrMcChicken