Search the Community

Showing results for tags 'Pmod'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 190 results

  1. Hello, I've posted the next part in my FPGA graphics series using the Arty + VGA Pmod or Basys 3. It shows you how to make use of double buffering to animate sprites using simple Verilog. https://timetoexplore.net/blog/arty-fpga-vga-verilog-03 Feedback very welcome, Will PS. I'll add the source to GitHub shortly.
  2. Hello, I am using Arty-Z7-10 board with 3 Pmods (NAV, GPS and RTCC), while there are only 2 JTAG ports available on the board. So, I decided to buy one of these 2*6-pin JTAG splitter cables and divide one of my JTAG ports between PmodGPS and PmodRTCC (since both of them need only one row of JTAG). Now, I am trying to make a block design and connect both of them to one JTAG, but it does not seem to be feasible. When I connect the first Pmod to the JTAG port, it occupies the whole port and it does not allow me to add another Pmod to it. Is this something I have to do in Verilog, and modify my XDC file? or is there an easier way to do it by just dragging and dropping the IPs in the block design? Best, Mahdi
  3. I am trying to connect my PMOD MTDS to the Zybo Z7, without Arduino. I have integrated the IP files, connected it via block diagram, and set up a FAT32 microSD with the 2 files that are needed also. When trying to connect to Vivado I can seem to figure out how to get to the console for which I can do MTDS Firmware code so I can do a custom UI. Documentation does not help much with connecting this PMOD. Please advise if you're familiar thanks.
  4. I am using a pmod GPS with a zybo z7-10 board. However, even after running the sample code for the GPS, nothing is being printed on the serial monitor. I'm not entirely sure whether I have connected the pmod right, since there are 6 pins on the GPS but 12 pins on the pmod port. Nowhere has anyone mentioned whether one should connect the pmod GPS on the top six pins or the bottom six pins. Am I doing something wrong here or is there some other problem? I have also attached a picture of my block diagram for reference.
  5. Hello all, I have a question pertaining to my ZedBoard. I'm running Linux on the PS using the built in SD card slot. I'm simultaneously building an isolated system in the PL, currently consisting of a Microblaze running a baremetal application. Now I'd like to run Python in the PL without touching the PS setup. Could I use the SD card Pmod to persist Linux to run on the Microblaze? I know I can't touch the existing SPI since it belongs to the PS, and I'd also like plenty of storage. Thank you for your time
  6. Hello I bought one PmodAD5, and tried to change its output data rate. I know sample rate can be changed by mode register value;However, how can i make changes to highest value(4.8kHz) of mode register in code. Thanks.
  7. Dear all, I'm trying to integrate Pmod GPS on my Xilinx ZCU102 platform with a Linux OS. To do so, I'm using the resources available in Digilentinc's vivado-library zip (PmodGPS_v1_1 IP + software drivers using xuartns550). I managed to make it work correctly in polling mode (calling GPS_getData func) with a clock freq of 49.995 MHz and a baudrate of 9600 symbols/s. Nonetheless, when I try to increase the baudrate to 115200, the NMEA messages in the ->recv buffer get corrupted. For instance, some messages are not correctly formatted because one comma has been flipped to another char and it makes the GPS_formatSentence function to seg fault. It's really important for my project to achieve higher rates (I'm working on a 60 fps camera and I would like to associate a GPS data to each frame and can not afford to spend too much time in the GPS_getData function in I want to preserve real time operation). Here are the hypothesis I make on the cause of this problem: a) The clock at both ends of the UART link are not synchronized. As far as I understand, this problem can also occur at low baud rates so it's probably not the main cause (cf PercentError computed in XUartNs550_SetBaudRate). b ) There is corruption on the physical link (my PMOD in connected to the ZCU102 using female-female jumper wires). Here are the workaround I tried so far: a) Check the checksum of the NMEA message before calling GPS_formatSentence and discard corrupted messages. This improve the reliability of the system but some problems still appear from time to time which is definitely not acceptable. I feel like it will be quite complex to design a check that is able to handle any kind of corruption (what if a $ sign or a * gets corrupted ?) b ) Use baud rate = 9600 and call GPS_getData and GPS_formatSentence in another thread (so that the main thread is not waiting for GPS_getData to complete). Unfortunately, I only have little experience in multi-threaded programming and I did not manage to make it work properly. I also think it's not very good practice, it would be better to make it work at higher baud rates. Do you have any complementary idea about how to fix that ? Thanks in advance, Alexandre
  8. I recently started working on the zybo z7-10 board. I have two pmods - the PmodGPS and the PmodCON3. Both of these pmods have 6 pins each and I want to connect both of these pmods to the same port on the fpga. However, I could not connect the PmodGPIO_0 and the PmodGPS_0 blocks to the same port in my Block Design in Vivado. Is there any way to do this?
  9. Hello everyone,I bought PMODDA1, but I don't know how to set PMODDA1 to make two DAC work at the same time in SDK and output 4 channels, and demo on GitHub can only output two channels,I would be very grateful.
  10. I need a second ethernet port on my Nexys4ddr board, so I got the PMODNIC100 ethernet connector. To get started, I was trying to follow the Getting Started with Digilent Pmod IPs Tutorial, but since I do not find any IP core for PMODNIC100 in Vivado 2015.4, I do not know how to proceed. Can you please guide me regarding how to send and receive data through the PMOD NIC100 ethernet connector?
  11. Hello! In the hardware user's guide of the ZedBoard I read the following: "Four Pmod connectors interface to the PL-side of the EPP. These will connect to EPP Bank 13 (3.3V). One Pmod, JE1, connects to the PS-side of the EPP on MIO pins [7,9-15] in EPP MIO Bank 0/500 (3.3V). Uses for this Pmod include PJTAG access (MIO[10-13]) as well as nine other hardened MIO peripherals (SPI, GPIO, CAN, I2C, UART, SD, QSPI, Trace, Watchdog). Two of the Pmods, JC1 and JD1, are aligned in a dual configuration and have their I/O routed differentially to support LVDS running at 525Mbs." My question is: Can I use ALL of those Pmod ports to connect the external ADC add-on boards "Pmod AD1" and "Pmod AD2" to them? Or can those ADC add-on boards only be used with a certain type of Pmod port, for example only with a Pmod connector that is connected to the PL, only with a Pmod connector that does not have differentially routed conductors for LVDS, etc.? Best regards!
  12. 1116345

    Pmod Ad5

    Hello I am using the Pmod AD5 to convert my analog signals from light sensor to be able to feed it into the fpga. Any one has an idea of how can i proceed? I tried by testing the AD5 by inputting an analog input but i cannot get to the digital output...any help would be highly appreciated..Thanks
  13. Here are 22+34=56 pins and I must add 4 pmods. How to declare in the IP INTEGRATOR pairs of pins as a Pmod entry?
  14. Hello, I am trying to use the pmod DA4 with my Arty S750 board. I'm aware that Digilent does not offer an IP for interacting with the Pmod, so I took it upon myself to design one. Anyways, things seemed to be going well until I actually tested the DA4. I know that the DA4 uses SPI to communicate, so I programmed the IP to communicate that way, and it does (outputs from the pmod connector correctly seen on an oscilloscope), but every time I connect it to the DAC I can't get much of anything to come out of the channels. I've read through the AD5628 reference manual, but a few things were ambiguous to me. First the commands on table 9. I don't really understand the difference between writing to the register (command 0) and writing to the DAC channel (command 3), and which I should be using for my project. And second, I plan on using an internal voltage, and it says that setting up the internal voltage is the first step. As I have it now, it's the first thing my program does and I'm afraid that the DAC is unable to read this input (maybe I should add a brief delay? I saw a brief delay in the "simon says" code). I know it's been a long post, but any answers or insights on the DA4 or any other part of my post is much appreciated. Thanks, Gill
  15. Hello, I am trying for a couple of days now to understand the pinout of pmods when used on a minized. I would like to use the Vivado-library for but I am facing a number of problems. I hope to be able to connect a 12 pins pmod (oledrgb) to one port and 2x 6 pin pmods (encoder and buttons) to the second one I understoody that I have to make a xdc file to manually connect them since the board is considered "custom" (so no xml, although I tried to edit one) and because I need 2 pmods to a single port.In the block diagram when I make the pmod connector external I get a pmod connector which includes connections like: PIN1_O Pmod_out_pin1_o\ PIN1_I Pmod_out_pin1_i\ PIN1_T Pmod_out_pin1_t PIN2_O Pmod_out_pin2_o\ PIN2_I Pmod_out_pin2_i\ PIN2_T Pmod_out_pin2_t and apparently comes from a file called board.xit and apparently means in, out and tristate for each pin. My question is how do I make a simple constraint file for these? Can someone provide an example. Why does it have to be so complicated? I mean surely I can "guess" if each pin is an input output or tristate from the module datasheet, but I am only considering how to route the pmods to their respective pin package so why should it matter? I tried to find a specific example including these pins names but failed to do so. Thank you for your help.
  16. Hello, Digilent vivado library ( https://github.com/Digilent/vivado-library) is not supporting for Virtex ultra-scale + (VCU118), The board can support for the MicroBlaze and PMOD Can you please help me out?
  17. Hi everyone, In this opportunity I want to establish a SPI communication between two PmodACL and a Zedboard, in Vivado software I done it this way: And I got the Bitstream file without any mistake. But how can I do the SDK configuration for read two PmodACL at the same time?
  18. I am very new to Raspberry pi and I need help regarding my R-Pi and Pmod ACL2 I would just like to test the functionality of the SPI connection and that's it I am not allowed to install any software I should just use the configure terminal I have installed the spi-dev on my R-Pi and I can't seem to find the ACL2 I'm sure I have connected them correctly Pls help Thanks in Advance
  19. hello i need some guidelines to know where to connect the output of pmod .Even i run connection automation i didnt get that.pls let me know where to give the output for interfacing acl
  20. Hi, I’m considering about VGA output device. About Pmod VGA, There are 2 questions(confirmations). Is this device manufactured from this schematic? Are there any other schematics? https://reference.digilentinc.com/_media/reference/pmod/pmodvga/pmodvga_sch.pdf In the following page’s demo, is the View Result Pmod VGA’s output result definitely? If it’s possible, please give me other Pmod VGA‘s output result(s). https://reference.digilentinc.com/learn/programmable-logic/tutorials/arty-pmod-vga-demo/start https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-z7-pmod-vga-demo/start Thanks.
  21. I would like to transfer data from nexus 4 DDR board to basys 3 board using pmod. What connection I have to do?
  22. I've recently started working with the VGA Pmod, but was having the oddest issue. Output looked correct, but colours were interchanged. I assumed I was doing something stupid in my Verilog or constraints file, but after further testing came to the conclusion that the spec sheet was wrong about the colour pins! This seemed extremely unlikely, a programmer who blames the hardware is almost always mistaken, but then I inspected my board, which is labelled rev C. The labelling of pins on my Pmod didn't match the spec sheet or images on the Digilent web site: my green and blue pin labels are interchanged (see photos below). So I tried updating my constraints to match my board labelling, but the results were still wrong! I actually get the correct output if I do the following: Where the spec says green I use red Where the spec says red I use blue Where the spec says blue I use green You can see an example of a constraints file at the end of this post which works on my board. I have also got a friend to test this on his recently acquired VGA Pmod and he gets the same behaviour as me. Can someone from Digilent comment on this and update the spec on the web site to save other users confusion? Digilent Web Site: rev B My VGA Pmod: rev C ## VGA Pmod rev C ## VGA Pmod Header JB set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0] }]; set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1] }]; set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2] }]; set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3] }]; set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0] }]; set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1] }]; set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2] }]; set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3] }]; ## VGA Pmod Header JC set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0] }]; set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1] }]; set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2] }]; set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3] }]; set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS_O }]; set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS_O }];
  23. Hello I want to send an image from nexys4 DDR to basys3 through pmod. Is it possible? If yes then how to connect them. Nexys4 DDR will be master device.
  24. spartacus28

    Pmod ALS

    Hi, I am new to this forum so still getting used to things. I am trying to implement the Pmod ALS on an FPGA, and I require to comply with the SPI protocol. I understood the protocol, but the only problem I have is this. "The PmodALS reports to the host board when the ADC081S021 is placed in normal mode by bringing the CS pin low, and delivers a single reading in 16 SCLK clock cycles. The PmodALS requires the frequency of the SCLK to be between 1 MHz and 4 MHz. The bits of information, placed on the falling edge of the SCLK and valid on the subsequent rising edge of SCLK, consist of three leading zeroes, the eight bits of information with the MSB first, and four trailing zeroes." As far as I know, 3+8+4=15, and not 16, so where is the extra clock cycle and what is it doing? Is the sensor providing 4 irrelevant numbers before the 8-bit of information and then 4 irrelevant numbers again? Any help will be appreciated. Thanks.
  25. peepo

    PMOD ACL

    Where are the reference design verilog HDL files for the Diglent PMODAcl adxl345 or adxl362 accelerometers on the latticesemi icestick? they are mentioned in various documents, but I did not find source files nor documentation. I did find Nexys3 & Zedboard