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  1. I was reading Dan Gisselquest's blog (aka @D@n), in particular, this specific part of the one that goes into some detail about the ALU for his ZipCPU: always @(posedge i_clk) if (i_ce) begin c <= 1'b0; casez(i_op) 4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB 4'b0001: o_c <= i_a & i_b; // BTST/And 4'b0010:{c,o_c } <= i_a + i_b; // Add 4'b0011: o_c <= i_a | i_b; // Or 4'b0100: o_c <= i_a ^ i_b; // Xor 4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR 4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL 4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR 4'b1000: o_c <= w_brev_result; // BREV 4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO 4'b1010: o_c <= mpy_result[63:32]; // MPYHU 4'b1011: o_c <= mpy_result[63:32]; // MPYHS 4'b1100: o_c <= mpy_result[31:0]; // MPY default: o_c <= i_b; // MOV, LDI endcase end else // if (mpydone) // set the carry based upon a multiply result o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0]; Dan makes the comment: "Each of the blocks in this figure takes up logic when implemented within hardware. As a result, even if i_op requests that the two values be subtracted, all of the other operations (addition, and, or, xor, etc.) will still be calculated. These other results, though, are just ignored. Thus, on the final clock of the ALU, all of the operations have been calculated, but only the result of the selected operation is stored into the output register." (bold emphasis mine) I found this a very interesting comment. Dan shows how there is effectively a multiplexer based on the opcode on the output of each of the logic chains. It strikes me that this is quite a waste of power, in general, so I wondered how, or even if it is possible to do things differently. Using one of the ZipCPU ops as an example, could one reliably implement something like the following? always @(posedge i_clk) if (i_ce) begin do_cmp_sub_op <= (i_op == 4'b0000) ? 1'b1 : 1'b0; ... rest of the op codes go here ... always @(posedge do_cmp_sub_op) begin {c,o_c } <= {1'b0,i_a}-{1'b0,i_b}; do_cmp_sub_op <= 1'b0; end There are many reasons why this is not something you would do in real life in a CPU, among other downsides it would have the effect of adding extra logic and an additional (at least) 2-clock latency right as the rising edge of the various do_xxxx registers would be one cycle behind, plus you'd need another cycle to turn the clock off so that you could catch a rising edge. So clearly this isn't something one would do for CPU ops that only take 1 cycle. 1) What are the various ways to only have some of the gates / logic working in a system while most of it is quiescent and only run when needed? 2) Does an if statement have the same logic as the case in this respect, i.e. does the logic for i_ce is 1, and i_ce is 0, also both get run but discarded on the input side of a multiplexer as well? 3) What are the options and tradeoffs involved in deciding what to use as the triggers for logic?
  2. peelza


    Hi I have been trying to transfer data via axi dma using zed board from pas few weeks. i am using the following codes for kernel driver and user application but for some reason the transfer is unsuccessful. Any help is appreciates Best regards,
  3. Hi all, May I humbly ask the experts in this forum if you already tried to implement AT commands into FPGA to make the cellular module works and be able to use the internet inside the FPGA. Ours, want to implement the cellular module via RS 232 interface into the pmod zedboard. Hoping for some guidance on how to go through it. Thank you in advance. Best regards, Glenn
  4. Hi I want to transfer data from PL to PS via DMA. I am using zedboard. I am using petalinux in the PS. i have created a module for the DMA called "axidma". i have a header file in the module named axidma.h where i have defined some macros. axidma.h and axidma.c are in the same directory. Now i want to use those macros in user space applicatiion but i cannot access them. I know it is possible by changing the makefile of the module but i am not an expert in makefiles so i dont know how to do that. Any help will be appreciated
  5. Good afternoon everyone, I was wondering if someone implements a filter in an FPGA in VHDL language, but that was designed and generated by the FILTER DESIGN HDL CODER tool (Matlab). To help me with some doubts. Thanks
  6. Hi there I am selling my Zinq-Z1 board ( zynq 7020 ) She is "as new". I put Arty Z7 in the title because these two board are so similar (not the same colour of pcb, and the Pynq has one thing more: a mic) mine is a pynq. My price is 99€ plus shipment , you can find easily on ebay my announce, there are some photos, I also sell on ebay my Spartan 6 board (papilio duo and computing shield) Thx & Regards B.
  7. Good morning everyone, I am currently developing a computer application in Matlab with help of VHDL and the Nexys 4 DDR, my problem is that I need to send a vector of 16 or more bits through an aurt module, the aurt module only sends 8 bits but I need to send more bits. anyone have any idea how to receive more than 8 bits per aurt? , I know that you should make the matrix reception module in vhdl and I was trying with this module that I have, but it does not work, and I have no idea how to do it to receive matrix. thanks. recepción.txt
  8. Hi, Can I use a CMOD A7 to run co-simulations using Vivado System Generator? In previous versions of System Generator it was possible to add custom boards. Is there a way to do it in Vivado?
  9. I want to list of small parts of processor and it's size like adder ,comparator ,etc ,please help me with it .
  10. Hello everyone and nice to meet you. I am a user of Zybo and until today everything was fine. But today I tried to use this board with a BLDC motor control board and something went wrong... The motor was not connected to the board, but battery was. The goal was to check correct operation of the MOSFETs (by PWM) at the control board and check it with oscilloscope. When I didn't see what I wanted to see, I turned Zybo off and back on, but it didn't turn on. The symptoms are as follow: - Short circuit between VCC3V3 and GND; - All other voltages are not short circuited; - The voltage converter seems ok too. Unsoldered R259 (zero Ohm resistor between converter's output and other circuit), but short circuit still remains. - Resistance of the pin used for PWM (to control MOSFET hi-driver) is infinite; - Zener diode connected to this pin changed its internal resistance as well (unsoldered it but it didn't change anything); - All other PMOD pins have finite resistance ~600 kOhm; - The PWM pin was surely connected to an input pin of the MOSFET driver. Is there any way to check if it is a permanent internal damage of FPGA without unsoldering it or not? I am pretty sure it happened because of that PWM pin but don't know why exactly. It might happen because of static discharge (though Zener diode should protect against it) or incorrect connection somewhere else by accident. Thank you for your time. Hope to get some hints soon. Regards,
  11. Got it under student edition from the university for a course. Used for 4 months only.
  12. Hi, I am using windows OS and want to know the use of USB port on Zybo board. I have no idea how it works. Can I able to implement using verilog or I must need Zynq processor? I appreciate if anyone have sample project which will describe the use of USB port using zybo board on windows OS. BR ALI
  13. Hi, I have a Zybo board and am using Vivado 2017.2. I have successfully written a number of VHDL modules allowing me to access the boards push-buttons, LEDs and slide switches using only the PL part of the device. I wondered if it was all possible to drive the LD_MIO LED from the FPGA? From my understanding it should be possible using the EMIO but have not been able to find an example or tutorial that shows how it is done. Regards FarmerJo
  14. I have an arty z7 FPGA an am working on a petalinux project. I am able to config and build my project. But when i boot it it says bitstream is not compatible with the target. What does that mean? any suggestions? I exported the HDF from vivado and in project settings the target device is same as the one i am using.
  15. Hi people, What I mean is that, can I write a program such that it can program the FPGA while executing? Thanks!
  16. Hi everyone, I am working on a project about drone. The project is sending and receiving data through UART and controlling the four brushless servo motors by getting these value for the speed of servo motors. I could find and combine codes for accomplishing the communication between fpga and the computer. However, I cannot make a relationship between coming data with servo motor. I get the coming UART data one by one by converting integer for duty cycle. Could you help me out this, how can I get the received data and send it to servo motors? Thanks in advance.
  17. etownsend

    Cmod A7 Clocking

    The schematic diagram for the Cmod A7 shows a clock with part number ASEM1-100.000MHZ-LC-T, which is a 100MHz clock. However when I look at the actual clock component it says it's 12MHz chip, which I confirmed by scoping the output. Is there any way to get a 100MHz clock signal out of this board?
  18. Tonight I discovered that this is a fast way to divide by 10 unsigned div10(unsigned x) { #ifdef REF /* Implement 32-bit division using divide */ return x/10; #else return (x * 0xCCCCCCCDLLU)>>35; #endif } Just wanted to post it here in case it becomes of use to somebody. A variant It could most likely be used with a DSP48 block to divide shorter (20 or 23 bit) binary numbers with much less resources and latency than a 10-bit binary divider.
  19. Hi, I am trying to rebuild the arty z7 petalinux BSP as per the instructions given by them here But when I try the command $ petalinux-boot --jtag --prebuilt 3, I get an error saying [skaat27@localhost Digilent-Arty-Z7-Linux-BD-v2016.2]$ petalinux-boot --jtag --prebuilt 3 ERROR: No subsystem configuration file can be find in the project. sh: lsb_release: command not found webtalk failed:Invalid tool in the statistics file:petalinux-yocto! webtalk failed:Failed to get PetaLinux usage statistics! Anybody knows what the issue is? Karthik
  20. skaat27

    Arty Z7 HDMI IN issue

    Hello Guys, I just received my Arty Z7 board and I was trying out the HDMI_IN design. I exactly followed the given instructions and I get this place_design error in vivado and "The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace." in sdk. I tried out the HDMI_OUT and it was working perfectly fine. I have attached the screenshots. Kindly help me out here. Note: I have seen similar questions on this forum, but none of those solutions helped me. So starting a new thread. TIA Regards, Karthik
  21. hello, I want to interface zedboard(PL-Section) with external ad7768-4 ADC board using SPI interface via FMC_LPC connector. i have following questions: 1) how i can set SPI interface in zedboard (i mean, where i can assign "sclk, cs#, sdi, sdo" pins from ad7768-4 adc board to zedboard(PL-section) ) ? 2) can I access QSPI Flash by using PL-section of zynq 7000 ? 3) what is the meaning of QSPI Feedback, where it should be connected? 4) can i use QSPI in standard mode ? please help me ! Thank you
  22. Good afternoon someone knows how to implement a UART communication protocol in l nexys 4 for the XADC, someone who can explain it to me and how to implement it?
  23. I have a Z-Turn FPGA, based around a Xilinx Zynq 7020. Unfortunately, its JTAG port is 2x7 with 2.54mm pitch. I just realized the HS3 uses 2.00mm pitch. Is there a recommended way to convert the pin pitch? I designed my own board, but an existing option would be more convenient.
  24. I am currently using nexys 4, I want to input console inputs to my VHDL design. I know that ISE uses a .ucf file where the inputs and outputs of the card are assigned, however my interest is not to use the inputs provided by the card and I do not know how to assign these inputs sent from an application, I would thank anyone who can help.
  25. Hello, We are a company based in Pittsburgh, Pennsylvania, and we are looking for a contractor who has experience with FPGA design work. Thank you.