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Found 338 results

  1. Regarding the the board Artix-7 (CMOD-A7) - https://reference.digilentinc.com/reference/programmable-logic/cmod-a7/reference-manual The datasheet says there is an 12 Mhz clock input and says the input clock can drive MMCMs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. My question is, if I want an output clock signal to be 1 Mhz from this FPGA to some external hardware, would I have to do a clock computation (Convert 12Mhz to 1Mhz) in my verilog logic? Just want to clear that out, thanks.
  2. I've created a block ram generator(single port ROM) in vivado using a coe file in verilog. I'm able to read the values one at time using continuous statement(able to instantiate rom block once a clock pulse). Here is my snippet: module coedata(clk,rst,a); input clk,rst; output [31:0]a; wire[12:0]addra,out; wire [31:0]douta ; count c1(clk,rst,out); // just gives count in 'out' to access address(addra) assign addra=out; blk_mem_gen_0 your_instance_name ( .clka(clk), // input wire clka .addra(addra), // input wire [12 : 0] addra .douta(douta) // output wire [31 : 0] douta ); assign a=douta; endmodule This is ok. I can read value through instantiating once a clock. But I want to store all these values into 2D wire such as [31:0] a[0:100].I want all the values to be available in one clock pulse.(Just assume we have created a sufficient ROM block) module coedata(clk,rst); input clk,rst; reg [31:0]a[0:99]; wire[12:0]addra,out; wire [31:0]douta ; count c1(clk,rst,out,i); // just gives count in 'out-binary' to access,'i-integer' address(addra) assign addra=out; blk_mem_gen_0 your_instance_name ( .clka(clk), // input wire clka .addra(addra), // input wire [12 : 0] addra .douta(douta) // output wire [31 : 0] douta ); assign a=douta; endmodule It is saying that 'i' is not a constant. Thanks in advance.
  3. For the ARTY A7 - 35T board, it possible to choose a clock in the constraints file that is greater than 100MHz?
  4. Nikhil Singh

    FPGA projects

    Can anyone suggest me some good beginner level projects which i can implement on spartan 3 fpga kit using VHDL. I have some projects in mind like the implementation of 8-bit microcontroller in fpga. But is the project too complex is think.It would be great if anyone can suggest me how to begin.Thanks in advance.
  5. I'm trying to develop a video pipeline on the Zybo platform that takes HDMI video in passes it to a custom IP and outputs the new video through VGA. I manage to create a system that takes HDMI and passes the video straight out the VGA interface but when I add in the AXI stream to video IP blocks in I can't seem to get a video out of the VGA. I tried tying all the rst_n and enable on the vid_in_axi4s, axi4s_vid_out and tc off to one but still doesn't output any video on the VGA. I also output the locked signal from the axi4s_vid_out IP to one of the LEDs on the board and it never gets set high. Does anyone have any idea what I might have setup wrong or if I'm missing something?
  6. Hello, I've posted the next part in my FPGA graphics series using the Arty + VGA Pmod or Basys 3. It shows you how to make use of double buffering to animate sprites using simple Verilog. https://timetoexplore.net/blog/arty-fpga-vga-verilog-03 Feedback very welcome, Will PS. I'll add the source to GitHub shortly.
  7. Hi all, i want to interface RGB(24 -bit) display with zynq 7000. How can I do this. I don't have any idea about how to do this. Can anyone help me .
  8. Caleb

    Im completely new to this

    Hi, I'm just getting into programming FPGAs and I've made my first program "blinky light" but I cant get my computer to either find the FPGA when connected or I'm missing a step when I set up Vivado. I've ran the Synthesis, Implementation, and generated the bitstream and everything completed without any errors. I just need to know how to do last part which is to put the code on the FPGA. Thanks! What I'm using/running: Ubuntu 18.04 (OS on my computer), Vidado WebPack, Arty A7 35t, and if it helps I programmed it in Verilog
  9. Greetings. I just started out VHDL not long ago,and not quite familiar with Moore FSM. So I was trying to write this Moore FSM code as shown in Picture of my initial sketch(Link to imgur,safe to click). after search for some reference about Moore in VHDL,I'm still stuck. I'm hoping someone can help me fill-in the missing pieces of my code and to fit into the sketch. Sincerely Appreciate. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity M6B is Port ( clk : in STD_LOGIC; x : in STD_LOGIC; rst : in STD_LOGIC; --z : out STD_LOGIC_VECTOR (6 downto 0); AN : out STD_LOGIC_VECTOR (1 downto 0); ledout : out STD_LOGIC_VECTOR (6 downto 0)); end M6B; architecture Behavioral of M6B is type state_type is (s0,s1,s2,s3,s4,s5); signal state : state_type; signal ledbcd : std_logic_vector (3 downto 0); signal ledonc : std_logic_vector (1 downto 0); signal osc : STD_LOGIC_VECTOR (24 downto 0); signal refresh_counter: STD_LOGIC_VECTOR (16 downto 0); signal oscen : std_logic; signal dispn : std_logic_vector (6 downto 0); begin process (clk,rst) begin if rst = '1' then state <= s0; elsif (rising_edge(clk)) then case state is when s0 => if x = '0' then state <= s1; else state <= s0; end if; when s1 => if x = '0' then state <= s2; else state <= s1; end if; when s2 => if x = '0' then state <= s3; else state <= s2; end if; when s3 => if x = '0' then state <= s4; else state <= s3; end if; when s4 => if x = '0' then state <= s5; else state <= s4; end if; when s5 => if x = '0' then state <= s0; else state <= s4; end if; end case; end if; end process; process (state) begin case state is when s0 => AN <= "10"; ledout <= "0000000"; when s1 => AN <= "10"; ledout <= "0000111"; when s2 => AN <= "10"; ledout <= "0000000"; when s3 => AN <= "10"; ledout <= "1001111"; when s4 => AN <= "10"; ledout <= "0000000"; when s5 => AN <= "10"; ledout <= "0000111"; end case; end process; end Behavioral;
  10. Hello everyone I am selling my almost brand-new Xilinx Nexys 3 Trainer Board w/ Spartan 6 FPGA. I've only used it for about 1 week and it is in absolute Mint condition. I am choosing to sell it because my new job at a startup uses Altera's line of products so I will be getting an Altera FPGA Unfortunately I just got my Nexys 3 so I am try to get whatever money I can for it. A link to this product on the Digilent site can be found below: https://store.digilentinc.com/nexys-3-spartan-6-fpga-trainer-board-limited-time-see-nexys4-ddr/ As you can see, it's worth $270 on the website, the total comes to over $300 if you order it from the store. I was hoping I could get around $200 if possible but am definitely open to haggling depending on the demand. Please let me know if you are interested! This is a great board to build projects and can do a ton of things! Inbox me or comment here
  11. I recently started working on the zybo z7-10 board. I have two pmods - the PmodGPS and the PmodCON3. Both of these pmods have 6 pins each and I want to connect both of these pmods to the same port on the fpga. However, I could not connect the PmodGPIO_0 and the PmodGPS_0 blocks to the same port in my Block Design in Vivado. Is there any way to do this?
  12. zazou

    HDMI_IN Arty Z7-20 ERROR

    Bonjour, J'ai testé le code du projet HDMI_IN publié sur le GitHub d'ici sur la version 2016.4 de Vivado et j'ai eu cette erreur ! any Help !
  13. Hi, I am working to establish a Measuring unit for testing FPGA board. I have used Artix-7 Device in the Basys3 FPGA board. My system is automatically measure ring oscillator frequency for the 5s duration of various location. I have used a counter to measure the frequency and showing in the 7-segment display for 5s and reset it after 5s. After 15s next ring oscillator is going to run and showing the same thing. I have successfully implemented and checked for three different Basys3 FPGA board. But the problem is that now it is not working for another three new Artix-7 Devices which I have bought just one month before. Same Verilog program is working in my previous three board but not working for the new three boards. Each operation, I have run 10 ring oscillator sequentially with each for 5s but after running one ring oscillator properly, then another ring oscillator has been gone to zero or sometimes not stop properly at the specific time. I have used the case statement to run individual ring oscillator. Please help me where is my main problem. I think in frequency counter function the clock from ring oscillator showing some problem but why is does not shown in other three FPGA board. The problem shows me very interesting but also painful to fix up it. Thanks
  14. Bonjour, je travail cette période sur le hdmi_out de la carte fpga arty z7-20, et comme tout le monde j'ai commencé par télécharger le fichier tuto de .git, deja apres l'implémentation y a rien qui s'affiche sur le deuxieme écran donc j'ai essayé de modifier les blocs IP par l'ajout d'un bloc qui convertit une image à une matrice et le lié avec le reste des blocs en appliquant les modifications nécessaires sur le BD et le .vhd , finalement, j'ai obtenue cette erreur. Remarque à savoir : j'ai vérifié les liaisons en RTL design et elles me paraits correctes MErci pour vos aides, translated by google translate by JPEYRON Hello, I work this period on the hdmi_out of the art7 zp-20 fpga card, and like everyone else I started by downloading the .git tutorial file, already after the implementation there is nothing that appears on the second screen so I tried to modify the IP blocks by adding a block that converts an image to a matrix and binds it with the rest of the blocks by applying the necessary modifications on the BD and the .vhd, finally, I got this error. Note: I checked the links in RTL design and they seem correct to me MErci for your help,
  15. Riesenrad

    SPI TFT Display

    Hello everybody. I recently got this SPI TFT display for my Raspberry Pi: https://www.conrad.at/de/raspberry-pi-display-modul-schwarz-rb-tft32-v2-raspberry-pi-a-b-b-raspberry-pi-1380381.html http://joy-it.net/tft-display-3-2-v2/ But I'd have more use for it in an FPGA project of mine. Now, I couldn't really find a pinout but as it's made for Raspberry Pi I could already figure out what lines are already reserved for power and with a little bit of luck, the MOSI / MISO / SCLK / Chip Select run on these pins: https://de.pinout.xyz/pinout/pitft_plus_35 I just wanted to know whether anyone has done this already and / or knows the pinout. Also, what could happen if I put data / voltage on the "wrong" pins? Also, is there something like an IP block that you can use for this type of stuff or would I need to write everything by myself? Thank you in advance! I've never used a display (except VGA) with my board so that's why I ask all these questions....
  16. Hello guys, I need two clock outputs operating at 6 GHz with an adjustable phase difference. Is it possible to obtain such outputs with Genesys 2 kintex-7 FPGA? I could not find anything related to this in the manual. Regards, pnsak.
  17. Ignacas

    FPGA audio - ADC and DAC

    Good day wizards, I've tried to introduce myself here, but now I would like to ask for a comment on my thoughts. My goal is to master audio processing (mainly routing and level controls for a beginning) on FPGA. The diagram will be very simple: Audio signal generator => ADC => FPGA => DAC => Analyzer (Spectrum, THD, Level) Audio signal generator will be made of two NE555 clocks with different frequencies (say 1kHz and 15kHz) to have a difference between L and R channels. ADC will be CS5381 ([email protected]), I2S output. DAC will be CS4390 ([email protected]), I2S input. (later maybe something better, but for now I'll use whatever I have in a drawer). Once I get this AD-DA conversion running properly, I'll try routing output of the ADC to my ARTY A7 input and pass that signal directly to the DAC. At this point I would like to see a low noise, low jitter signal passing thru. Next step could be mixing L and R signals together, adding more converters generating AES/SPDIF signals on FPGA, etc.. But at very beginning, I have a fundamental problem with clocks. I want to run this setup at 48kHz, so I obviously need this clock and 48k*256=12.288MHz MSCLK. Playing around with PLL Clock wizard didn't gave me the desired result (still + or - couple MHz). I understand that it would not be a massive problem and I could run any weird frequency, but there will be a sync problem with external digital equipment if I get around to do, say AES/SPDIF interface. Finding XTAL trimmed to 12.288 is not a problem, but can I just hook it up to any desired pin and use it? I have also seen some posts (if I got it right) discouraging of using multiple clocks as it can get messy (inter-sync problems?). Before I dive into this, I would appreciate Your insights and critics. I will post all my story here as soon as I have something to share with You:) Thank You!
  18. 5v dc motor is not rotating when I connect to pmod ja0 and it is working fine when I connected to vcc and gnd in the pmod ja. anyone can help me .. ???
  19. I tried to synthesise the Zybo HDMI In project https://github.com/Digilent/Zybo-hdmi-in for the latest Vivado 2017.4.1. Without changing anything from the Block design and just upgrading all IP Cores in order to start the synthesis, the timing will not be met: Slack: - 6.327 ns The IP Cores are generated globally. How I can fix this problem?
  20. hello, I am interested in the following reference design: https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-vga-test-pattern-with-mouse-overlay/start The design currently does not provide any sources: Is this project abandoned? I believe it had not been updated since 2015. Is there a later version available (this one, perhaps, or on github?) I am interested in the USB host with mouse, which I intend to implement on the Zybo/Zybo-Z7. Do you provide the sources for this project? Is there a project you can recommend, There is also the BIST for the Zybo-Z7, maybe it contains relevant references? thank you
  21. I run the httpserver on an Arty board and I get in console WiFi Connection Established Dynamic begin Is Linked to the physical network Link status: 0x0 Timeout occured Shutting down Resting for 30 seconds 30 seconds until restart 10 seconds until restart Done resting WiFi Connection Established Dynamic begin Is Linked to the physical network Link status: 0x0 Timeout occured Shutting down Resting for 30 seconds 30 seconds until restart 10 seconds until restart Done resting WiFi Connection Established Dynamic begin Is Linked to the physical network Link status: 0x0 Not Initialized Hard Error status 0x10011007 occurred. Shutting down Resting for 30 seconds 30 seconds until restart 20 seconds until restart So I don't get anymore Network initialized .What can cause this problem?The Pmod also overheats.
  22. Hi everyone, this is my very first question on your forum I'm new to the FPGA topic and this week I struggled to evaluate how difficult the following project will be: We have a motion capture system tracking a hand and driving a very complicated levitation device. The project should work with as little delay as possible. At the moment it is about 17 ms and the target is to reduce this to around 7 ms. Most of the latency comes from the GigE connected cameras, sampling at 200 Hz, but also from the operating system. Because of the complex computation, the difficult part is precomputed as a very big lookup table (8 GB) present in memory. To reduce latency, we want to work 'bare metal' and later on , eliminate the lookup table and use high parallelized code to drive 128 devices at 50kHz frequency. What I planned so far: Using the existing cameras would require a low latency system handling image processing (stereo camera registration and key point tracking). I know that these would be efficient to be implemented on an FPGA. To address 4 Optitrack Prime 13 cameras, the NetFPGA-1G-CML Kintex-7 FPGA Development Board looks very promising. Can somebody estimate how difficult it will be to extract images of a GigE Camera with the Vivado Studio will be? The second part is frustating: I do not know how to add DDR3 RAM from a laptop to this setup. Is it possible to add an adapter to the FMC and use the MIG to configure the Interface? I tried to search for this but only found boards with SO-DIMM sockets or RAM -Chips presolderd. The first are far to expensive and the second have not the required capacity. I only used SPI and I2C on a microcontroller so far, therefore interfacing ethernet phy or RAM programmatically and especially physically is still a mystery to me. The third problem is optional: the target device is interfaced via USB 2 and drivers only exist for Windows. It is not easily possible to communicate directly with an FPGA in this scenario is it? In the end, I want to use high level programming, like the Vivado Studio or Simulink. The project is financially limited, but around 2000 Euro would be adequate, my professor told me. I am thankful for all constructive advices, comments. literature and questions. Please tell me your opinion, if an FPGA will be the right choice, the project is manageable and/or if there is a better solution. Best regards from Germany, Matthias Popp
  23. Hey evryone ! i am using zybo 7010 in ubunto 16.04 I generate a BOOT.BIN and an image.ub, I put the two files in the SD card but it does not boot! in vivado i activate UART0 and UART1. jumper is good. I enclose the two files system-user.dtsi and system-conf.dtsi. my serial terminal is /dev/ttyUSB1. please helpe ! system-user.dtsi system-conf.dtsi
  24. Hi all, I m beginner in Fpga, actually i dont know anything in FPGA. Last week I bought a zybo z7-10 board from diligent store. I want to run a linux on this borad, for that i did everything as per the tutorial link:http://www.instructables.com/id/Setting-up-the-Zybot-Software/ And i installed linario in the sdcard. I only have a VGA monitor to connect to zybo, so that i used a vga to hdmi converter and boot the zybo. But i cant see nothing in the screen except the text "Input Not Supported". Three leds in the board is lighted up and glow still. I dont know , whats the actual problem with this? Can anyone help me... Thanks in advance
  25. Hi all, I m a beginner in FPGA(zync 7000). I want to implement a project which took images from two cameras, one with usb(uvc) interface and one with csi-2 interface. One thing to note that i not using both cameras simultaneously. Only once at a time(Switch over whenever required) With first USB camera, i want to do some image proseesing functions like filtering and CLAHE(Contrast-limited adaptive histogram equalization) on the captured image. Then the processed is images is displayed on a HDMI or RGB interface mini projector(DLP 2000). Here i indicated both HDMI and RGB interface because of i need to test the performance of both interfaces with HDMI input projector and RGB input interface TI DLP 2000 mini projector. And I also need to display the image which is captured from the second CSI-2 camera and do a little enhancements, then display it in a DSI 5 inch LCD screen(51 pin MIPI DSI) the details link of cameras , projectors and lcd is given below USB Camera: http://www.elpcctv.com/mi5100-5mp-usb-camera-module-usb20-aptina-125inch-color-cmos-sensor-100degree-lens-p-221.html CSI-2 Camera: https://www.waveshare.com/product/rpi-camera-f.htm DLP 2000 RGB - projector: http://www.ti.com/tool/DLPDLCR2000EVM HDMI projector: https://www.ebay.in/itm/302673956725?aff_source=Sok-Goog Display : https://www.alibaba.com/product-detail/5-inch-720p-oled-display-720_1925219941.html?spm=a2700.7724838.2017115.42.6ba11d77AqfGq7 Can anyone please help me to build this project. Just give some basic idea like 1. which zynq version is suitable for this application? 2. Board design, start from scratch zynq design or any SOM modules having zynq 7000 3. Hard core or soft core ip? 4. best evaluation board for this design? I also need suggestions for above said questions. I want to do this in an industrial design way, so that i m asking help from others and I m just a beginner in this field, expecting good support from this forum. Great thanks in advance....................