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Found 304 results

  1. Hi, I need the .iic file in order to upload the eeprom IC5, where the Cypress CY7C68013A firmware is stored, by means of CyConsole tool. Currently IC5 does not assert the USB-ON signal, which enables the power on the board. Sincerely, Radek (rsip)
  2. HI, Is their example code on how to use DEPP module of the Adept SDK in National Inst CVI.
  3. Hi there, i a newbie. I hope i am asking the right questions. I have been trying to figure out what kind of hardware/software is needed for my project. The project is getting the images with a high speed image sensor with a frame rate of 500-1000fps at a lower resolutions such as 160x120 or 480x360 pixels. The frames will be read or saved with FPGA SoC board. I know that I have an option of given interfaces: Option 1: Board level image sensor with FFC Cable (LVDS or MIPI CSI-2 interface) Option 2: Boxed camera with USB3.0 Cable interface I would love to think about the option 2. The Basler acA640750um USB 3.0 camera with ON Semiconductor PYTHON 300 CMOS sensor. This camera has a frame rate of 751 fps at VGA resolution. So if I have a FPGA board with a USB3.0 this option would be okay for plug and go ? I hope someone will lead me and help me. Regards, Sirac
  4. Hello, so I followed this axi-dma tutorial and everything looks pretty fine. Now, this tutorial only goes to running a HelloWorld application inside de XSDK. I would like to know how t write something to DDR and how to read something back (specifying addresses e.g.)? To be precise this is how the actual design looks like I would really appreciate some sample C code of how to instantiate (?) the AXI Slave/Master ports to be able to read something from the DDR. Thanks !!
  5. Hello guys, Some time ago I've watched a talk of the nand2tetris course/project. If you've never heard of it you can check it out here: http://www.nand2tetris.org/. Basically it is a course designed to build a computer from the very ground up. It starts with logic gates and goes all the way up to programming a small game project (hence the name nand2tetris). I've always been curious about doing something with FPGA hardware, but never had any idea of a feasible, yet interesting-result-yielding project. Well, as you can probably guess, up until now that is. During my university days I attended an FPGA workshop and I've read some stuff about the hardware components and the available course material such as Basic Introduction and Design flow of Programmable Logic Device FPGA. If you need to pick up something relating to the PLD or FPGA, you can check it out here: http://www.apogeeweb.net/article/67.html. So I think I kind of have an idea about the difficulty of the project. But since everything I've been reading just made me more excited, I decided I absolutely want to give this a shot. Now there's a lot of FPGA information out there, so I'm surely still missing a lot of important information, but I would like to get started and think the best way to learn is to actually experiment with a real FPGA instead of wasting too much time with HDL simulations only to become used to functions that aren't going to synthesize on the board anyway. So I now would like to ask you about some things I'm still unsure about and would like to have clarified before buying an expensive development kit. I've read several articles about Altera and Xilinx and right now my choice would be a Spartan 3E Starter Board - this one to be exact: https://store.digilentinc.com/spartan-3e-starter-board-limited-time/ The main questions I'm having right now: Is there a general reason that would argue against getting the Spartan E3 board? I actually have no idea how powerful an FPGA really is, but assuming it's running on Cyclone II hardware, it probably should run on a Spartan 3 as well? Or is that in itself already a stupid question, as FPGA comparison doesn't work so easily? In general, who is more newbie-friendly, Altera or Xilinx? (I've worked with VHDL before, which I think is Xilinx, right? Altera's Quartus is probably very similar?) From how I understand the FPGA toolchain, in the above linked offer there should be everything included to get me going. right? I also have this second candidate: http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,400,836&Prod=ATLYS Maybe I'm an idiot, but as I read the offer, *only* the board is sold? I.e., in contrast to the first offer, I would need additional stuff to get something running on the board? It also strikes me as a mayor drawback that there is not really an output option besides a few LEDs. which for me would be very annoying; I'm already unhappy about the board linked before *only* having a small display (which in itself, however, is awesome to have of course). This might also be a stupid question: I remember from back in the FPGA workshop I mentioned that getting a number-display to run is not that hard at all. How much more effort is it to get something displayed on a screen (either an attached one or a PC screen accessed via one of the available ports)? And as a final question: I've also seen some very much smaller boards than the ones linked here, that are also much cheaper. Are the boards I'm looking it overkill for what I'd like to do with them? Or does actually the contrary hold, and such a project wouldn't even run on one of the smaller boards available? Regards, Joshua
  6. Hello, I am using xilinx spartan 6 sp6-x9 board in which its led's and switch works on active low logic. Is it possible to convert switch and leds to to active high logic
  7. ATIF JAVED

    ADC DAC SELECTION

    I want to interface DAC and ADC with some fpga evaluation board My requirement of ADC and DAC is following DAC input ->sampling_rate=2MS/s frequency=455khz ADC Input ->Signal bandwidth=400khz i have no problem of resolution So someone please guide me or refer me some models of adc and dac along with some FPGA evaluation board that complete my requirements . Also refer me if anyone know about some board that have build in adc dac along with FPGA Any kind of help in this regard would be much appreciable
  8. I want to know how to connect a speaker and it's frequency in fpga board.how to send the data to the speaker...?? Suppose when a lift is go to 1st floor it should make a sound like 1st floor like that . Thanks Vamsi
  9. I am gonna start a project with the following setup (attached the overview). I am doing a scaling function on the FPGA. I was thinking about the Nexys Video Development Board. This board got an DP output. But it only has HDMI as input/output. I know that HDMI is almost DVI. I don't think I can use an adapter. I need the DVI-connector and not HDMI-connection. Prioritized is the DVI--> FPGA--> DP connection. Next comes DP--> FPGA--> DP. I need the DVI input according to the picture. I have been reading about a FMC DVI I/O on Avnet but I can not find it. Any help to solve this hardware/component setup would be much appreciated! (Which FPGAs and FMC to use) Regards
  10. Hi, I want to program my KC705 board with raspberry pi. I have downloaded adpet utilities and adept runtime on raspberry pi. I know python programming but I am not very fluent with c coding. If anyone can help me with programming following modules it will be really helpful to me. programming FPGA with bit files. programming flash with bin file(or any other file format) If possible loading mfs files or elf files on DDR memory.
  11. Hello Digilent, I am just going to buy an ARTY A7 35T board and I have to interface an external ADC ADC7091R with it. I know it has an on board XADC but I need to do for some specific purpose. Now I have seen a Pmod of ADC7091 R given in its datasheet and I want to know that "DO ARTY A7 support pmod of ADC7091R". Thanks
  12. What is Digilent providing to support Labview connectivity to your latest FPGA boards? The older Nexys3 board had the Adept software and Labview driver that allowed Labview to communicate to the FPGA board as if it was a simple parallel interface. This is no longer supported by your latest FPGA boards from what I can see. So what do you provide to allow Labview to talk to your FPGA boards?
  13. Hi, I've got my Arty sending out UDP packets to my laptop, without any soft CPU involvement. I've still got to add checksums and so on, but at least it works! http://hamsterworks.co.nz/mediawiki/index.php/ArtyEthernet
  14. I am attempting to build upon the hdmi demo, here is what I want to accomplish: Take over PMOD_C port as a general purpose digital output (8 pins) Here is what I have done (aside from debugging for hours) I dropped down and wired a PmodGPIO_0 block in my design and connected it to PMOD_C (JC), used the auto-connection automation function in Vivado. The build seems to work just fine, exported hardware, etc as normal. In SDK I get a drivers/ directory in hw_patform_1 with PmodGPIO_v1_0 and everything looks fine. Here are the exact steps I followed from here to where I am now: copied PmodGPIO.h down to hdmi/src (build project directory) copied code (functions) from PmodGPIO.c into video_demo.c (build main .c) copied code (init, main, close) from output_demo.c into appropriate places in video_demo.c Question 1) The code would not execute, because it appears the XPAR_ for PMODGPIO does not feed correctly into xparameters.h. Is this normal? I tried to workaround by checking system.hdf and found the base address for my PMODGPIO 0x40000000 and hard-coded it. This would allow the code to compile, but it does not run correctly, it hangs in GPIO_begin on the statement Xil_Out32(InstancePtr->GPIO_addr+4, bitmap);. This is the first statement where it attempts to write to the mapped memory. I have a feeling that something with the PmodGPIO IP is not building correctly for me, but I don't know how to correct it. I have tried several times to clean and rebuild the project, but again I don't know if I am taking the right steps. Question 2) Is there some type of 'build' that I need to do in SDK or somewhere else to initialize the IP correctly and be able to write to the PmodGPIO ? Thanks!
  15. What is the best software to program in C++/C an Arty board? I tried Vivado HLS but it is good only for algorithms not for the components of the board. The SDx made by Xilinx is not compatible with the boards. If are others programs can someone please provide tutorials/books for some examples in C.On Xilinx forum I couldn't find any tutorial for working with the board components in C.
  16. Hi, I've a requirement to interface a CMOS Image sensor(MT9P006) with Artix7 FPGA. I've to perform image processing including autofocus and interfacing with USB 3.0 peripheral controller IC. Is it possible with artix7??? If yes, then what are the tools (like vivado ISE etc) required and what will be the expected cost for those tools... Is there any free software alternatives for them??? Thank you...
  17. I am using basys 3 and VHDL to create a stopwatch and I need to do it for both the 7 segment display of the basys3 itself and for a external 4 digit 7 segment display. I am given the clock divider code for the 7 seven of the basys3 by my instructor and I managed to do the stopwatch. When I changed all my constraints to the PMOD pins and connect to the external 7 segment I can see that it works because it stops and resets but it does the counting so quickly that I can't read at all. I am thinking that the problem may be because of the clock divider and the frequency of the clocks. The given code states that since the original clock of the basys3 is 100 MHz a counter will count up to 500000 to obtain a 100 hz and another counter will count up to 208334 that is 240 Hz. First of all I didn't understand why the second clock is 240 Hz and why do the counters count up to these irrelivant numbers. Secondly what can I do for the external 4 bit 7 segment to slow it down?
  18. Hi, I just brought the NEXYS 4 FPGA and want to start learn it myself. The first project I am trying to do is changing the seven segment display one by one. Is there any example code that I can start with? Thank you.
  19. Hi t all, actually I new to programming, some places may be completely unknown, but a period of time, I need to do some procedures to detect, but appear in the process of the problem is not so easily solved for me, so I want to seek some help. I have designed a system using Artix-7 FPGA on a custom board. The goal is to transfer 32 bit data to an external on-board chip whose data bus is an inout port. First, a little background: The external chip is driven by a 100MHz clock which is generated by the FPGA, let's call it o_clk. The FPGA generates this clock through an MMCM in the Memory Interface Generator (MIG IP) using the 200MHz differential system clock. The o_clk is looped back from the FPGA's output and is given to another ball as an input clock, let's call it i_clk. The external chip receives the o_clk and sees data on this clock's rising edge. However, when the external chip sends data back to FPGA, the FPGA sees this data on the looped back i_clk. The idea behind doing so is that we can treat communications as source synchronous, in both the directions (remember, it is an inout port). Something like below: FPGA --> EC is synchronous to FPGA because FPGA generates clock EC --> FPGA is synchronous to EC because FPGA gets external clock (virtually from EC) To constrain this design, I have used the i_clk to set input delays on the io_data and have used the o_clk to constrain output on the same io_data bus. I have made sure I am using a forwarded clock (create_generated_clock)(using the ODDR2) for the set_output_delay constraint. Here are my constraints: create_clock -period 10.000 -name i_clk -waveform {0.000 5.000} [get_ports i_clk] set_clock_groups -name loopback_grp -asynchronous -group [get_clocks i_clk] -group [get_clocks o_clk] set_input_delay -clock i_fx3_pclk -max 8.000 [get_ports io_fx3_fdata] set_input_delay -clock i_clk -min 2.000 [get_ports io_data] set_output_delay -clock o_clk -max 2.000 [get_ports io_data] set_output_delay -clock o_clk -min -0.500 [get_ports io_data] The system seems to work properly when I run it on hardware, but I still have some doubts because I am still an amateur FPGA developer and this is my first big FPGA design. My questions are: Have I designed a good system? Is it correct to treat the communication from EC http://www.kynix.com/Detail/390575/EC.html --> FPGA as source synchronous? (The other direction is source sync because FPGA is providing clock, if I am not wrong.!) Are my constrains correct? Many thanks!
  20. Hello, I am working on a project using an Z7-20 FPGA for computer vision processing using a CMOS camera sensor. I am planning to run convolutions on the image data for usage such as a Sobel filter. (to avoid RAM requirements, I will most likely use a Line Buffer to store the data while it is in use. This means I will need a camera sensor which can connect directly to the FPGA and outputs one pixel at a time (through multiple wires for each color), with a well-defined (or customizable) clock to synchronize the data transmission. I want like something cheap, rugged, and easy to wire like the OV7670 (as this is for a robot, I cannot use something too sensitive to vibration), but something that has a little higher resolution and framerate (I was thinking 480p or 720p at 60fps, or 1080p at 30fps, but lower is fine if the price is too expensive), as well as being a breakout board which can be easily wired (I can make a custom pin header adapter from the camera module to the FPGA's ports if needed, but I don't want to have to use a very small/thin one or something that requires SMD soldering). Any suggestions? Thanks in advance.
  21. I am trying to load my program to a Block RAM using Data2mem, after the bitfile is generated. Here are the steps: I have generated a BLOCK RAM as single port ROM with 32 bit-width and 16384 bit-depth. Then translated the design without any BMM file and looked at the PlanAhead tool to see which BRAM are used and which ramloop is assigned. There are 15 ramloop lines. There are 14 PRIM36 primitives and 1 PRIM18 primitive as shown below: BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM18.SP **(RAMB18)** BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP **(RAMB36_EXP)** BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP) BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP) ⋮⋮ BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP (RAMB36_EXP) I wrote the following .BMM file for address the ROM from 0x0000 to 0xFFFF. and add it to the xilinx project. ADDRESS_SPACE pr_mem1 RAMB32 [0x00000000:0x0000ffff] BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_init.ram/SP.SINGLE_PRIM18.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[2].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; BUS_BLOCK ⋮⋮ BROM_instance/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[14].ram.r/v5_init.ram/SP.SINGLE_PRIM36.SP [31:0]; END_BUS_BLOCK; END_ADDRESS_SPACE; But when I tried to compile it again it gives me the error: ERROR:Data2MEM:29 - Inconsistent address space size in ADDRESS_SPACE 'pr_mem1'. Can you please help me out where the error is occurring? Is ramloop[xx] correctly used?
  22. Hello Forum , Its my first Post so I hope it helps everyone I have this code for generating a 25 Mhz clock having a 50 Mhz clock as main using the basys3 board. I use the LSB as the clock because it will goes 1/2 of the main clock of 50Mhz *//////////////////////* START OF CODE //Clock module clkdiv( input wire mclk , input wire clr , output wire clk25 ); reg [24:0] q; always @(posedge mclk or posedge clr) begin if(clr == 1) q <= 0; else q <= q+1; end assign clk25 = q[0]; endmodule *////////////////////////* END OF CODE So whenever I want to call it I just make a instance of this class. In Vivado, when I open my synthesized project and click [Tools ---> Edit devices properties] This is where I select my clock frequency as 50 MHZ { Please see image attached } So my questions are : Is this the proper way to set up a clock using Vivado and the Basys3 Board?In the main page of the Basys3 it says that one can get a clock as high as 450 Mhz but in the options of the [Tools ---> Edit devices properties] I can only find clocks as high as 66 MhzAnd just some basic ones Why Vivado takes sooo long to synthesized, implement and generate the bitstream of an easy and small code? Just implementing in hardware an AND gate takes me 5 minnutes to download the program to the board. Is there a quicker way ? Thanks Forum .
  23. Good morning, I am currently using the uart protocol to communicate my Nexys 4 DDR with Matlab, but I have the inconvenience that I need to send signals of more than 8 bits, someone knows how to receive matrices in vhdl by uart (something like the function fread de matlab). Thank you for your attention
  24. I was reading Dan Gisselquest's blog (aka @D@n), in particular, this specific part of the one that goes into some detail about the ALU for his ZipCPU: https://github.com/ZipCPU/zipcpu/blob/master/rtl/core/cpuops.v#L317-L343 always @(posedge i_clk) if (i_ce) begin c <= 1'b0; casez(i_op) 4'b0000:{c,o_c } <= {1'b0,i_a}-{1'b0,i_b};// CMP/SUB 4'b0001: o_c <= i_a & i_b; // BTST/And 4'b0010:{c,o_c } <= i_a + i_b; // Add 4'b0011: o_c <= i_a | i_b; // Or 4'b0100: o_c <= i_a ^ i_b; // Xor 4'b0101:{o_c,c } <= w_lsr_result[32:0]; // LSR 4'b0110:{c,o_c } <= w_lsl_result[32:0]; // LSL 4'b0111:{o_c,c } <= w_asr_result[32:0]; // ASR 4'b1000: o_c <= w_brev_result; // BREV 4'b1001: o_c <= { i_a[31:16], i_b[15:0] }; // LODILO 4'b1010: o_c <= mpy_result[63:32]; // MPYHU 4'b1011: o_c <= mpy_result[63:32]; // MPYHS 4'b1100: o_c <= mpy_result[31:0]; // MPY default: o_c <= i_b; // MOV, LDI endcase end else // if (mpydone) // set the carry based upon a multiply result o_c <= (mpyhi)?mpy_result[63:32]:mpy_result[31:0]; Dan makes the comment: "Each of the blocks in this figure takes up logic when implemented within hardware. As a result, even if i_op requests that the two values be subtracted, all of the other operations (addition, and, or, xor, etc.) will still be calculated. These other results, though, are just ignored. Thus, on the final clock of the ALU, all of the operations have been calculated, but only the result of the selected operation is stored into the output register." (bold emphasis mine) I found this a very interesting comment. Dan shows how there is effectively a multiplexer based on the opcode on the output of each of the logic chains. It strikes me that this is quite a waste of power, in general, so I wondered how, or even if it is possible to do things differently. Using one of the ZipCPU ops as an example, could one reliably implement something like the following? always @(posedge i_clk) if (i_ce) begin do_cmp_sub_op <= (i_op == 4'b0000) ? 1'b1 : 1'b0; ... rest of the op codes go here ... always @(posedge do_cmp_sub_op) begin {c,o_c } <= {1'b0,i_a}-{1'b0,i_b}; do_cmp_sub_op <= 1'b0; end There are many reasons why this is not something you would do in real life in a CPU, among other downsides it would have the effect of adding extra logic and an additional (at least) 2-clock latency right as the rising edge of the various do_xxxx registers would be one cycle behind, plus you'd need another cycle to turn the clock off so that you could catch a rising edge. So clearly this isn't something one would do for CPU ops that only take 1 cycle. 1) What are the various ways to only have some of the gates / logic working in a system while most of it is quiescent and only run when needed? 2) Does an if statement have the same logic as the case in this respect, i.e. does the logic for i_ce is 1, and i_ce is 0, also both get run but discarded on the input side of a multiplexer as well? 3) What are the options and tradeoffs involved in deciding what to use as the triggers for logic?
  25. peelza

    AXI DMA

    Hi I have been trying to transfer data via axi dma using zed board from pas few weeks. i am using the following codes for kernel driver and user application but for some reason the transfer is unsuccessful. https://github.com/mstuehn/dma_proxy Any help is appreciates Best regards,