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Found 337 results

  1. in my design i need to calculate an array containing a waveform, (a sine for this example) inputs of the block would be a memory containing an index of 1024 samples and a user-related period value. output would be an array of 1024 samples written on ram being amplitude and phase fixed the expression to calculate the single sample of the waveform would be x = sin ( period * index (0-1023)) Could I instantiate 1024 blocks so that the samples of the resulting array could be calculated concurrently?
  2. Pier

    Zybo z7 evaluation

    How could be possible to implement the design shown in attached video? in the video the arrays are 600 samples each, but i would go for bigger arrays as possible and 24 or 32 bit values i'm planning to use a zybo z7 board exxample.mp4
  3. Hi. I've tried to operate Pcam-5c at Zybo-Z7-zynq7020 using Xilinx Vivado tool. I refered to source code for Pcam-5c posted on github( ). It operated successfully but I want to try again using other camera module instead of Pcam-5c. I have some problems in MIPI formatting data because Zybo7020 & Pcam-5c use RAW10 data but my camera module use RAW12 data. How can I use RAW12 format with Zybo-Z7-20 ?
  4. I am looking to start developing a new setup and I purchased the USB104 A7 and Zmod ADC1410 as shown in the picture and can not find a simple way to get this up and running to see if it meets my criteria. The ones that are linked there are for a different development system and require an Ethernet port. Can you guide me to the proper resources? Best, R
  5. Hi, I'm a newbie trying to learn about the Genesys 2 board and would like to program the onboard OLED as an exercise. I'm following this tutorial. There is a prominent warning that says "Important! Make sure to turn off the OLED display before shutting down or reprogramming your board." Why? What will happen if I don't turn off the OLED display and simply turn off the power switch? Will it get damaged? This makes me very nervous to try my own programs since I will probably mess up at some point. Can someone reassure me that I won't do any permanent damage? Thanks!
  6. Dear friends, We have intended to use the JTAG-SMT3-NC module for both FPGA and ARM MCU programming. Our planned configuration is channel A for FPGA programming and channel B for ARM MCU programming. Do you please notify us if we are capable to perform the above work or not? Also, can we configure as JTAG the both channels (A and B)of the JTAG-SMT3-NC module with FT_PROG software. If not, please advise the solution. Also you can submit your tender to eliminate this difficulty. Attached please find the our working configuration. Wait for your response. Sincerely yours,
  7. Hey, I have a very novice question and really just need a high level answer, but I'll get straight to the point! I'm using the Zybo z7-10 with Vivado and Vitis 2019.2. This is what I would like to do, and I'm trying to do it in VHDL: Write some data from software to control registers that I define Perform some processing on this data Use DMA to write some results to DDR I would like the firmware piece that does the processing to be a block in the BD. I've gone through many forums, and it seems at one time the preferred way was to package an IP. I found out about adding an RTL module, which seemed more appropriate because I want to be able to modify quickly as I go, and in the same project. Based on what I've read, I was thinking to make an RTL module with a Slave AXI-lite interface (not sure how to do the registers though?), then use a master AXI-stream to pump the results to a Xilinx DMA IP block. I've been passing Synthesis but getting different Implementation errors ("failed to stitch checkpoint", "*.vhd is a black box") doing trial and error with this. All I've done in terms of the code is try to define the entity port to have those two interfaces, either copying from other IPs or using the Language Template (for AXI stream). Is there a good example in VHDL of a barebones AXI peripheral like this, that will pass Implementation? Once that works, I can get into adding those registers and the processing logic. Thank you!
  8. Hello, I have a NetFPGA 1G-CML board and in my new project I will have to use Vitis Accelered Libraries. So, I would like to know if I can use Vitis Accelerated Libraries on a NetFPGA 1G-CML board. If I can't use it on NetFPGA 1G-CML, what would be the best board option? Thank you
  9. Hello, (FPGA board is Nexys A7 100T) So my end goal is to implement RC4 stream cipher and implement it onto FPGA. I was trying to configure a switch that will utilize the 7-segment 8- digital display and display my original plain text. And another switch that will display the encrypted text. I have attached the sources and test benches below that works. And have screen captured the simulation to show the results. Thanks for spending the time, I'll be high alert for response and try to respond on follow up questions. Can someone help me with this?
  10. Due to the nature of my project, I need to program the cmod a6 with the use of a JTAG programmer. I have a HS2, which is configured AND recognized by iMPACT AND Adept. Unfortunately, when I attempt to program the cmod a6 board, I get the following: // *** BATCH CMD : Program -p 1 -dataWidth 4 -spionly -e -v -loadfpga INFO:iMPACT:583 - '0': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '0': Device IDCODE : 00001111111111111111111111111111 INFO:iMPACT:1579 - '0': Expected IDCODE: 00000100000000000000000010010011 PROGRESS_START - Starting Operation. INFO:iMPACT:583 - '1': The idcode read from the device does not match the idcode in the bsdl File. INFO:iMPACT:1578 - '1': Device IDCODE : 00001111111111111111111111111111 INFO:iMPACT:1579 - '1': Expected IDCODE: 00000100000000000000000010010011 PROGRESS_END - End Operation. Elapsed time = 0 sec. When I use Adept, I get this: ===== Digilent Adept ===== Adept System Rev 2.7 Adept Runtime Rev 2.20 Adept Application Rev 2.4.2 Copyright © 2010 Loading board information... Warning: Could not find specific board information Initializing Scan Chain... Default information loaded. Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Found device ID: ffffffff Initialization Failed. ------------------------------------------------------------------ I've soldered the header to the J4 holes on the CMOD A6 correctly. I know that this board work because I've programmed it when I connected it DIRECTLY to my Windows laptop's usb port, by way of cable. Am I missing a file? I did put the DLL files in the proper place and was able to have iMAPCT able to see the HS2's SN. Why is this not working?
  11. Hello all: we are using FT2232H on our boards to emulate the JTAG cable such it is recognized by Xilinx tools, ISE and Vivado. The most convenient solution is to use the Digilent driver which is already provided with Xilinx tools. I wonder what is the exact configuration of the FT2232H to enable using this driver? Could you please share the details? Thank you, Wojtek SkuTek Instrumentation
  12. I'm at a complete loss trying to get the Arty A7-100t onboard DDR-SDRAM to behave reliably. Let me start by telling you what I've done (maybe some of this will be helpful for others): The Arty A7-100t is running totally unmodified (no PMOD, ChipKit, etc.). I've generated a Memory Interface Generator (MIG) IP core as per Digilent's recommendations: Digilent MIG Resources My XCI and PRJ files: ddr_sdram_mig.xci and ddr_sdram_mig.prj I've written a simple DDR SDRAM Interface module, based on the approach found on Numato. Unlike the reference code, my Verilog reads incoming addresses and reads / writes to RAM (or at least it should): ddr-sdram-interface.v I continually read from the aforementioned memory interface via the following code: always @(posedge clk_100mhz) begin if (readReady) begin readAddr <= readAddr + 1; end end assign led = readData[7:0]; I write to the memory (first all zeros, then all ones, then the address) via the following code: always @(posedge clk_100mhz) begin if (writeReady) begin writeAddr <= writeAddr + 1; if ((writeAddr == 0) && (writeCounter < 3)) begin writeCounter <= writeCounter + 1; end case (writeCounter) 0: writeData <= 32'h00000000; 1: writeData <= 32'h11111111; 2: writeData <= {8'h00, writeAddr}; 3: writeEn <= 0; endcase end end Now for the problem: If I run the Verilog above exactly as-is, the LEDs show total garbage (randomness). If, instead, I continually write (the same) data to memory over-and-over again, eventually the LEDs will start flashing the binary counter I expect. This tells me that the read mechanism is functional, but the write is extremely unreliable. Any insight would be most appreciated. I purchased the Arty A7-100t in part because it has the DDR3 memory. I understand that there are significant performance issues (due to the -1 speed grade of the Artix-7 chip), but I expect to be able to attain reliable read / write behavior at low-speed.
  13. Totally new to all this. 73 year old grandpa, retired engineer, returning to grad school, microelectronics concentration. Lots of technology catch-up to do. So, starting with VHDL. I must self-teach VHDL and need my first FPGA. Can someone help me understand these 3 possible choices for someone in my position: (1) Basys MX3 PIC32MX, (2) Nexys A7-100T, (3) Zybo Z7. Don't want to buy anything too complex, but I have to get the basics with ability to grow. Many questions about compatibility, accessories, programming... Can you help me get started?
  14. I tried to do this Pong game project and connect VGA to monitor. But monitor keeps flashing. Video im not sure if this problem appear because i have connected Basys3-> VGA adapter to hdmi -> wire hdmi to mini hdmi. Because my screen has only mini hdmi port.
  15. Hello all, I am new in this forum. I am using a ZedBoard Zynq-7000 Development Board (part#: xc7z020clg484) and familiar with Verilog modules/test bench as beginner. I've created a top module with an output 8-bit bus (OUTPUT) and multiple inputs. My inputs are CLK (from main clock of the board), RESET (push button), ENA (ON/OFF switch), stpGo (stop and go push button). Inside my top module I've three sub-modules instantiated and connected to each other. I created a constraint file to connect all the ports to the necessary switches or buttons on my ZedBoard Zynq-7000. Here is my constraint file: # Clock Source - Bank 13 set_property PACKAGE_PIN Y9 [get_ports {CLK}]; # "GCLK" # ---------------------------------------------------------------------------- # User LEDs - Bank 33 set_property PACKAGE_PIN T22 [get_ports {OUTPUT[0]}]; # "LD0" set_property PACKAGE_PIN T21 [get_ports {OUTPUT[1]}]; # "LD1" set_property PACKAGE_PIN U22 [get_ports {OUTPUT[2]}]; # "LD2" set_property PACKAGE_PIN U21 [get_ports {OUTPUT[3]}]; # "LD3" set_property PACKAGE_PIN V22 [get_ports {OUTPUT[4]}]; # "LD4" set_property PACKAGE_PIN W22 [get_ports {OUTPUT[5]}]; # "LD5" set_property PACKAGE_PIN U19 [get_ports {OUTPUT[6]}]; # "LD6" set_property PACKAGE_PIN U14 [get_ports {OUTPUT[7]}]; # "LD7" # User Push Buttons - Bank 34 # ---------------------------------------------------------------------------- set_property PACKAGE_PIN P16 [get_ports {RESET}]; # "BTNC" set_property PACKAGE_PIN R16 [get_ports {stpGo}]; # "BTND" # ---------------------------------------------------------------------------- # User DIP Switches - Bank 35 # --------------------------------------------------------------------------- set_property PACKAGE_PIN F22 [get_ports {ENA}]; # "SW0" #set_property PACKAGE_PIN G22 [get_ports {SW1}]; # "SW1" # --------------------------------------------------------------------------- # IOSTANDARD Constraints # Note that the bank voltage for IO Bank 33 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 33]]; # Set the bank voltage for IO Bank 34 to 1.8V by default. set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 34]]; # Set the bank voltage for IO Bank 35 to 1.8V by default. set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks 35]]; # Note that the bank voltage for IO Bank 13 is fixed to 3.3V on ZedBoard. set_property IOSTANDARD LVCMOS33 [get_ports -of_objects [get_iobanks 13]]; set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets stpGo_IBUF]; My constraint file is looking at my top-module ports only. I thought my other modules are internally connected and don't have to create constraint files for each of them separately. I am using Vivado 2018.2 software and I have attached the screenshots helping you to understand me better. Part#: xc7z020clg484-1 or ****-2 getting the same result. I restarted the Vivado and ran synthesize and implementation in order to generate Bitstream. Before all these steps I used this command to set Bitstream version check to "False" in my Tcl consul. After Bitstream generation was completed successfully (as system reported) I went to program my device but no Bitstream file was showing in dialog box to open. I browsed and selected a .bit file in my impl_1 folder called CountingLED.bit. I had the same error messages after I ran "Program". Please refer to images and let me know if I am not clear enough. Thank you for your helps in advance.
  16. Hello, this is my first post in this forum. Im working on a project which I should sample data from ADC (ADS5463), and then fft the sampled data and see the results. The sampling clock is 400MHz and my FPGA working with DRY clock coming from the ADC which is 200MHz (fs/2). Im sampling the data with DDR interface using Lattice IP (GDDRX1_RX.SCLK.Aligned Interface), which sampling 12 bit DDR data into a bus of 24 bit (there the 11:0 bits is positive edge data and 23:12 is the negative edge data). Next Im storing this data into 2 FIFOs, one for the positive edge data and another for the negative edge data. My next step which Im currently working on is to insert this data into the FFT IP module which Lattice provides. ( I attached timing digrams (timings.pdf). The FFT IP Im creating is 12bit width input/output so I need to time the input flags in a way that it take first data from the positive edge FIFO and the next data from the negative edge FIFO and processing so on in a stream. Of course Im paying attention to all the flags as the IP telling. I want to ask some guidelines questions about how to do it correctly. 1. Do I need a state machine which indicates when the FIFO is full and only then to read the data into the FFT input? Or I can start writing to the FFT without state machine and just counter register which indicate when is read enable asserted and start reading to the FFT? 2. Do I need to fill the FIFO and then read the data until its empty, or I can write to the FIFO and read from the FIFO to the FFT continuously? 3. Any guideline how to make this task correctly? I never did this before.. From my prepective I would just wait for ready flag from the FFT IP and read_enable from the FIFO and start to provide data to the FFT IP but I told the there is more timing managment to be made. thanks. timings.pdf
  17. I'm a newbie here and I’m working on a inverter test bench project where I have two three-phase inverters connected through an inductive load. The idea is to emulate in real time the behave of an electrical machine. To be clearer, the first inverter is going to be tested (Device Under Test) and the second one plus the inductive load must behave like an electrical machine. To do so, we are going to use a FPGA board, which must have the following specifications: - Capable to drive both inverters switching at 50kHz (each inverter has 6 MOSFETs switching at this frequency) - 20 digital I/O - 4 ADC with 16 bits (ideally) and 20MHz at least. The ADCs can be integrated or not in the FPGA board - Capable to communicate in real time with Matlab/Simulink - The board will be placed inside the test bench, in a temperature around 50°C We know that we are going to use Vivado to the VHDL coding, but we are not sure about the ADCs, regarding the Eclypse Z7 with the two Zmod ADCs. We want to code the least possible in VHDL (no VHDL coding if possible), so my questions are: 1) Are we going to have to code the ADC data acquisition? 2) Is the VHDL code generation done automatically by Matlab? I do have the toolbox for HDL coding. Our budget is around €1000,00. I would like to know if the board Eclypse Z7 with the two Zmod ADCs is a good choice for the application and if you have another advices it would be highly appreciated. I hope I made myself clear. Thank you!
  18. MoGamaal

    Display Variables

    I want to know how to display variables on PmodOLEDRGB from Sensors via artix-7 kit in vhdl
  19. Hello, I am working through some of the examples for the Arty A7 device. The device seems to come pre-loaded with firmware, some simple reference design that makes use of UART, LED's and pushbuttons. Is there some project I can download to reproduce this reference design? I am planning to overwrite this in the future, but I also wanted to have a copy. Thanks
  20. MoGamaal

    Pmod OledRGB

    I think my question is general but i want to know how to initialize Pmod OledRGB using case when-statment i found some vhdl codes using this method but i cant understand it
  21. i enter 5V in FFT so maybe the result are just on impulse signal. but actuality my result have unexpected -'128 signals' (263~390 cnt ) why does -128 apear. and how to disapear unexpected value (-128)
  22. Hello. My system clock on my arty z7-10 board is 125MHz. When I try to simulate this clk in my test bench with a single port RAM, it does not work, and only outputs zeros, however, the simulation does work with a 6.25MHz clock. I looked at the 7 series memory usage guide, and some other xilinx forums, and thye said the BRAM should be able to run at around 200 MHz, so I am not sure why my simulation doesnt. The first picture is the 6.25MHz clock and everything is running fine. The second picture is the 125MHz clock where nothing happens. Testbench is below and source verilog is attatched. Thanks. I also put this on the xilinx forums but accidently posted it in the wrong catagory, so I will put it here too. `timescale 1ns / 1ps module tb; // this testbench from timing diagram memory uage guide. wire [15:0] DO; reg [10:0] ADDR; reg CLK; reg [15:0] DI; reg EN; reg REGCE; reg RST; reg [1:0] WE; always #4 CLK = ~CLK; BRAM_SP_2048x16 uut(DO,ADDR,CLK,DI,EN,REGCE,RST,WE); initial begin CLK = 0; DI = 16'hDDDD; ADDR = 11'h000; EN = 0; REGCE = 0; RST = 0; WE = 2'b00; #1 EN = 1; #8 DI = 16'hCCCC; ADDR = 11'h00F; WE = 2'b11; #8 ADDR = 11'h07E; DI = 16'hBBBB; WE = 2'b11; #8 ADDR = 11'h08F; DI = 16'hAAAA; RST = 1; WE = 2'b00; #8 ADDR = 11'h020; DI = 16'h0000; RST = 0; EN = 0; #4 $finish; end endmodule 7_series_BRAM_SP.v
  23. We are trying to communicate between two PMOD BT2 modules. We first configured one module as master and the other as slave using SM command in tera term ,then we searched from the master terminal for the other device and we got the MAC of the other device then we tried connecting to the device using the SR command but we didn’t get any response. Can you help us resolve this issue?
  24. Hi, I am using the Embedded Vision Demo project for Image processing. I created a new filter by creating a new IP core for it in Vivado HLS 2017.4 (for the first time) referring to the filters used in the demo and then exported it. I added the new IP in the Embedded Vision Demo in Vivado 2017.4 and made the required connections followed by generating the block design. I was able to successfully complete all these tasks, however when I try to run the demo using Xilinx SDK 2017.4 (the same way I ran the demo prior to adding new filter) it does not read the switch change in hardware for this new filter thus not showing any results for it. The already present filters work in the same way as before. I am new to working with Xilinx SDK and Vivado HLS, kindly guide me if I am doing anything wrong and suggest me if any changes are to be done in the SDK files. bd.pdf
  25. I am completly new for the FPGA and basys3 development board. I have a project for Counter on the 7 segment displays on the board. We got 3 different layers as a design. cntr cntr_rtl cntr_top cntr_top_struc io_ctrl io_ctrl_rtl And in the project it has to diplay on the 7 segment controlled by the switches : count up / count down / hold / reset options: The priorities for these switches are: 1. reset 2. hold 3. count direction top level VHDL file cntr_top.vhd Port Name Direction Description clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset sw_i(15:0) In 16 switches pb_i(3:0) In 4 buttons ss_o(7:0) Out Contain the value for all 7-segment digits ss_sel_o(3:0) Out Select a 7-segment digit io_ctrl clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset cntr0_i(n:0) In Digit 0 (from internal logic) cntr1_i(n:0) In Digit 1 (from internal logic) cntr2_i(n:0) In Digit 2 (from internal logic) cntr3_i(n:0) In Digit 3 (from internal logic) sw_i(15:0) In 16 switches (from FPGA board) pb_i(3:0) In 4 buttons (from FPGA board) ss_o(7:0) Out to 7-segment displays of the FPGA board ss_sel_o(3:0) Out Selection of a 7-segment digit swclean_o(15:0) Out 16 switches (to internal logic) pbclean_o(3:0) Out 4 buttons (to internal logic) cntr.vhd clk_i In System clock (100 MHz) reset_i In Asynchronous high active reset cntrup_i In Counts up if signal is ‘1’ cntrdown_i In Counts down if signal is ‘1’ cntrreset_i In Sets counter to 0x0 if signal is ‘1’ cntrhold_i In Holds count value if signal is ‘1’ cntr0_o(n:0) Out Digit 0 (from internal logic) cntr1_o(n:0) Out Digit 1 (from internal logic) cntr2_o(n:0) Out Digit 2 (from internal logic) cntr3_o(n:0) Out Digit 3 (from internal logic) I will attach also the file to the attachment. Now my code is working and do all the funcitionality correct but there is only one issue which is the DEBOUNCE code part. I didnt use the clk signal for the code and i have to change it. The certain given clock signal has to be used. So can any be give me suggestions how i can correct the debounce concept in the code. io_ctrl_rtl.vhd -code down below: library IEEE; use ieee.std_logic_1164.all; use ieee.numeric_std.all; architecture rtl of io_ctrl is constant COUNTVALUE : std_logic_vector(16 downto 0):= "01100001101010000"; signal s_enctr : std_logic_vector(16 downto 0):="00000000000000000"; signal s_2khzen : std_logic :='0'; signal s_1hzen : std_logic :='0'; signal s_2khzcount : std_logic_vector(3 downto 0) := "0000"; signal swsync0 : std_logic_vector(15 downto 0):="0000000000000000"; signal pbsync0 : std_logic_vector(3 downto 0):="0000"; signal swsync1 : std_logic_vector(15 downto 0):="0000000000000000"; signal pbsync1 : std_logic_vector(3 downto 0):="0000"; signal swtmp : std_logic_vector(15 downto 0):="0000000000000000"; signal pbtmp : std_logic_vector(3 downto 0):="0000"; signal swdebounced : std_logic_vector(15 downto 0):="0000000000000000"; signal pbdebounced : std_logic_vector(3 downto 0):="0000"; signal s_ss_sel : std_logic_vector(3 downto 0) := "0000"; signal s_ss : std_logic_vector(7 downto 0) := "00000000"; begin -- rtl ----------------------------------------------------------------------------- -- -- Synchronize the inputs -- ----------------------------------------------------------------------------- p_sync: process (clk_i, reset_i) begin if reset_i = '1' then swsync0 <= (others => '0'); pbsync0 <= (others => '0'); swsync1 <= (others => '0'); pbsync1 <= (others => '0'); elsif clk_i'event and clk_i = '1' then swsync0 <= sw_i; pbsync0 <= pb_i; swsync1 <= swsync0; pbsync1 <= pbsync0; else null; end if; end process; ----------------------------------------------------------------------------- -- -- Generate 1 KHz enable signal. -- ----------------------------------------------------------------------------- p_slowen: process (clk_i, reset_i) begin if reset_i = '1' then s_enctr <= (others => '0'); s_2khzen <= '0'; elsif clk_i'event and clk_i = '1' then if s_enctr = COUNTVALUE then -- When the terminal counter is reached, set the release flag and reset the counter s_enctr <= (others => '0'); s_2khzen <= '1'; s_2khzcount <= std_logic_vector(to_unsigned(to_integer(unsigned( s_2khzcount )) + 1, 4)); else s_enctr <= std_logic_vector(to_unsigned(to_integer(unsigned( s_enctr )) + 1, 17)); -- As long as the terminal count is not reached: increment the counter. if s_2khzen = '1' then s_2khzen <= '0'; end if; end if; if s_2khzcount = "1010" then s_1hzen <= not s_1hzen; s_2khzcount <= "0000"; end if; end if; end process p_slowen; ----------------------------------------------------------------------------- -- -- Debounce buttons and switches -- ----------------------------------------------------------------------------- p_debounce: process (s_1hzen, reset_i) variable dbouncecntr : integer:=0; begin if reset_i = '1' then swdebounced <= "0000000000000000"; pbdebounced <= "0000"; dbouncecntr :=0; -- Change clocking the process with signal from sens list. else if (dbouncecntr = 0) then swtmp <= swsync1; pbtmp <= pbsync1; dbouncecntr := dbouncecntr + 1; elsif (dbouncecntr = 1) then if (swtmp = swsync1) then swdebounced <= swsync1; end if; if (pbtmp = pbsync1) then pbdebounced <= pbsync1; end if; dbouncecntr := 0; end if; end if; end process p_debounce; swclean_o <= swdebounced; pbclean_o <= pbdebounced; ----------------------------------------------------------------------------- -- -- Display controller for the 7-segment display -- ----------------------------------------------------------------------------- p_displaycontrol: process (clk_i, reset_i) variable v_scancnt : std_logic_vector(1 downto 0):= "00"; variable v_output : std_logic_vector(3 downto 0):="0000"; begin if reset_i = '1' then v_scancnt := "00"; s_ss <= "00000000"; elsif clk_i'event and clk_i = '1' then if s_2khzen = '1' then case v_scancnt is when "00" => v_output := cntr0_i; s_ss_sel <= "0001"; when "01" => v_output := cntr1_i; s_ss_sel <= "0010"; when "10" => v_output := cntr2_i; s_ss_sel <= "0100"; when "11" => v_output := cntr3_i; s_ss_sel <= "1000"; when others => v_output := "1111"; s_ss_sel <= "0001"; end case; case v_output is --ABCDEFG, when "0000" => s_ss <= "11111100"; --0 when "0001" => s_ss <= "01100000"; --1 when "0010" => s_ss <= "11011010"; --2 when "0011" => s_ss <= "11110010"; --3 when "0100" => s_ss <= "01100110"; --4 when "0101" => s_ss <= "10110110"; --5 when "0110" => s_ss <= "10111110"; --6 when "0111" => s_ss <= "11100000"; --7 when "1000" => s_ss <= "11111110"; --8 when "1001" => s_ss <= "11110110"; --9 when others => s_ss <= v_scancnt & "000000"; end case; if v_scancnt = "11" then v_scancnt := "00"; else v_scancnt := std_logic_vector(to_unsigned(to_integer(unsigned( v_scancnt )) + 1, 2)); end if; else null; end if; else null; end if; end process p_displaycontrol; ss_o <= not s_ss; ss_sel_o <= not s_ss_sel; end rtl; The code for : cntr_top_struc.vhd library IEEE; use IEEE.std_logic_1164.all; architecture rtl of cntr_top is component cntr -- component of cntr port (clk_i: in std_logic; -- 100 MHz system clock reset_i: in std_logic; -- async high active reset cntrup_i : in std_logic; --counts up if signal is '1' cntrdown_i : in std_logic; --counts down if signal is '1' cntrreset_i : in std_logic; --sets counter to 0x0 if signal is '1' cntrhold_i : in std_logic; --holds count value if signal is '1' cntr0_o: out std_logic_vector(3 downto 0); -- Digit 0 (from internal logic) cntr1_o: out std_logic_vector(3 downto 0); -- Digit 1 (from internal logic) cntr2_o: out std_logic_vector(3 downto 0); -- Digit 2 (from internal logic) cntr3_o: out std_logic_vector(3 downto 0)); -- Digit 3 (from internal logic) end component; component io_ctrl ---- component io_crtl port (clk_i: in std_logic; -- 100 MHz system clock reset_i: in std_logic; -- async high active reset cntr0_i: in std_logic_vector(3 downto 0); -- Digit 0 (from internal logic) cntr1_i: in std_logic_vector(3 downto 0); -- Digit 1 (from internal logic) cntr2_i: in std_logic_vector(3 downto 0); -- Digit 2 (from internal logic) cntr3_i: in std_logic_vector(3 downto 0); -- Digit 3 (from internal logic) swclean_o: out std_logic_vector(15 downto 0); pbclean_o: out std_logic_vector(3 downto 0); ss_o: out std_logic_vector(7 downto 0); -- Contain the Value for All 7-Segment Digits ss_sel_o: out std_logic_vector(3 downto 0); -- Select a 7-segment digits pb_i: in std_logic_vector(3 downto 0); --4 Buttons sw_i: in std_logic_vector(15 downto 0) ); --16 Switches end component; -- Declare the signals that are used to connect the submodules. signal s_cntr0 : std_logic_vector(3 downto 0); signal s_cntr1 : std_logic_vector(3 downto 0); signal s_cntr2 : std_logic_vector(3 downto 0); signal s_cntr3 : std_logic_vector(3 downto 0); signal s_cntrup : std_logic; signal s_cntrdown : std_logic; signal s_cntrreset : std_logic; signal s_cntrhold : std_logic; signal s_overflow : std_logic_vector(11 downto 0); begin --Instantiate the counter that is connected to the IO-Control i_cntr_top1 : cntr port map (clk_i => clk_i, reset_i => reset_i, -- cntrdir_i => s_cntrdir, --swsync_o(13); cntrup_i => s_cntrup, --swsync_o(13); cntrdown_i => s_cntrdown, --swsync_o(12); cntrreset_i => s_cntrreset, --swsync_o(15), cntrhold_i => s_cntrhold, --swsync_o(14), cntr0_o => s_cntr0, cntr1_o => s_cntr1, cntr2_o => s_cntr2, cntr3_o => s_cntr3); --Instantiate the IO control to which it is connected i_io_ctrl : io_ctrl port map (clk_i => clk_i, reset_i => reset_i, swclean_o(12) => s_cntrdown, swclean_o(13) => s_cntrup, swclean_o(15) => s_cntrreset, swclean_o(14) => s_cntrhold, swclean_o(11 downto 0) => s_overflow(11 downto 0), cntr0_i => s_cntr0, cntr1_i => s_cntr1, cntr2_i => s_cntr2, cntr3_i => s_cntr3, ss_o => ss_o, ss_sel_o => ss_sel_o, sw_i => sw_i, pb_i => pb_i); end rtl; Please waiting for your suggestions. Any help would be great appricated thanks for all. here down below example for debounce but couldnt find to way to implement. ----------------------------------------------------------------------------- -- -- Debounce buttons and switches -- ----------------------------------------------------------------------------- p_debounce: process (clk_i, reset_i) begin -- process debounce if reset_i = '1' then -- asynchronous reset (active high) elsif clk_i'event and clk_i = '1' then -- rising clock edge end if; end process p_debounce; swsync_o <= swsync; pbsync_o <= pbsync; ------------------------------------------------------------ Final Project-Decimal Count -1Hz.rar