Search the Community

Showing results for tags 'FPGA'.



More search options

  • Search By Tags

    Type tags separated by commas.
  • Search By Author

Content Type


Forums

  • News
    • New Users Introduction
    • Announcements
  • Digilent Technical Forums
    • FPGA
    • Digilent Microcontroller Boards
    • Non-Digilent Microcontrollers
    • Add-on Boards
    • Scopes & Instruments and the WaveForms software
    • LabVIEW
    • FRC
    • Other
  • General Discussion
    • Project Vault
    • Learn
    • Suggestions & Feedback
    • Buy, Sell, Trade
    • Sales Questions
    • Off Topic
    • Educators
    • Technical Based Off-Topic Discussions

Find results in...

Find results that contain...


Date Created

  • Start

    End


Last Updated

  • Start

    End


Filter by number of...

Joined

  • Start

    End


Group


AIM


MSN


Website URL


ICQ


Yahoo


Jabber


Skype


Location


Interests

Found 338 results

  1. This little module might be of use to somebody - it sends 16-bit values to an external serial device, as four ascii hexidecimal digits (eg "12AB"), with new lines and carriage returns. http://hamsterworks.info/index.php/Hw_tx_binary_as_ascii The sample design send the settings of the 16 slide switches every time the center button is pressed.
  2. Hi, I have been working on a PMOD TFT LCD that can be used to play video directly from the FPGA using only two PMODs. I designed the hardware a couple of years ago but recently I had to do a project where I needed to use the Vivado block diagram interface. I thought it was pretty cool how fast it was to put a design together so I went about making an IP Core that controlled the PMOD. It has an AXI Lite interface used to initialize the LCD and then a AXI Stream interface that can be connected directly to a VDMA core. I ended up making three different demos including the following: Using the Microblaze to write directly to the screen. I wrote another core that behaves like a console output that will write directly to the screen for you so the MCU doesn't need to write the console stuff to the screen. I streamed video. Unfortunately this was harder than I expected and had to use the Pynq board instead. Here's a video of it working. I wrote a project page on hackaday.io with more details https://hackaday.io/project/25333-pmod-tft-board I was thinking of trying to sell the boards but I didn't know if there would be any interest. Dave
  3. So, I am starting to get these errors during the Place & Route phase WARNING:Par:288 - The signal kbd<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<3>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<4>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<5>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<6>_IBUF has no load. PAR will not attempt to route this signal. it only started when I added the enb register. It really makes no sense. `timescale 1ns / 1ps module Trigger(trig,trigb,kbd); output trig; output trigb; input[7:0] kbd; reg trigb; reg trig; reg enb; always begin trigb = kbd[7]; end always @* begin case(kbd) 0: begin enb = 0; trig = 0; end 254: begin // line 0 trig = 0; enb = 0; // kbdphase = 1; end 253: begin // line 1 trig = 0; enb =0; end 251: begin // line 2 trig = 0; enb =0; end 247: begin // line 3 trig = 0; enb =0; end 239: begin // line 4 trig = 0; enb =0; end 223: begin // line 5 trig = 0; enb =0; end 191: begin // line 6 trig = 0; enb = 1; end 127: begin // line 7 if (enb) begin trig = 1; enb = 0; end else begin enb = 0; trig = 0; end end default begin enb = 0; trig = 0; end endcase; end endmodule The idea behind this is that the C64's Keyboard has 8 Column lines that get strobed individually. The row lines will return the keys that are pressed on that column (not implemented). Right now it just throws a line (TRIG) when a line goes high. The problem is that the line 7 does not behave like exactly like the others. It can actually go low for other reasons but never after line 6. So I thought to put up an enable pin to be turned on during line 6 period and then this will let line 7 know it can do its job and it can set the enable register go low again. Anyways, the ISE is giving me a terrible time. Also I can't understand why it requires me to set the enb line low on practically every single part of the case statement... otherwise I get it complaining about a possible latch. Do you all notice anything I am doing wrong? Thanks a lot for any help you can provide.
  4. FlyMario

    FPGA Clock

    I am learning how to program a FPGA (spartan) lately. The language I am using is Verilog which is not really important to this question. I have the FPGA connected to my Commodore 64 via Logic Level Converters. And I am having lot of success. I am reading 8 lines from the Keyboard port looking. My verilog is simply looking for a matching value on those lines. No problems at all. But I am curious, how is the logic managing to work when I have not really set up a clocking line. Is the FPGA using main clock to trigger events to move on in the FPGA. For instance, if you have a blocking statement it would seem that in order to get past that block, there must be some clock checking the incoming value before the logic can continue. Is this true? Or am I missing something. Is there a clock in the fpga that is pushing the logic along? Flymario
  5. mihai5

    IDS on zedboard

    Hi everyone, I want to implement an intrustion detection system on zedboard. I want to use PL for string matching and PS to handle the interrupts on possitive detection. Being a beginner in this area(FPGA + networking) I would like to know if this is possible and any informations or any type of instructions or steps that can help me is tremendously appreciated.
  6. Prompted by another thread here ( https://forum.digilentinc.com/topic/4180-mmcm-dynamic-clocking/ ), I've been experimenting the the Dynamic Reconfiguration Port on the Artix-7 MMCM You can find the code and constraints for the Basys3 here: http://hamsterworks.co.nz/mediawiki/index.php/MMCM_reset It might be of interest to somebody (e.g. to change a VGA clock frequency dynamically).
  7. Hello, I'm building this filter, generating a .COE file in Matlab, which I use in the FIR compiler IP. Here are two screenshots of the settings. Do you know if the difference between the two pictures, in terms of magnitude, are just a displaying fact or if there is a real amlpification involved by the FIR compiler ? If it's the case, do you know how to fix it to generate the same filter as I designed in Matlab, so without gain ? Kind regards, Yannick
  8. I was attempting to use the Board tab within a block design in Vivado 2016.4 to connect some of the board interfaces on a Nexys Video FPGA board. In particular, the HDMI In component goes and instantiates both the TMDS signals in, as well as the DDC signals out, and Vivado marks the HDMI In component as connected. However, when I go to synthesize or elaborate the design, I get a bunch of messages telling me that top-level ports have not been assigned to an IO, and if I open up the I/O Port window, I can see that there's no package pin assigned to the HDMI ports. The only package pins that seem to be assigned are the board clock and reset. I don't think it's a problem with the board files, since I can clearly see from the Board tab that the interfaces are there. And the tool did know which pins were connected to clock and reset. My concern is that it looks like the iostandard and loc properties in part0_pins.xml aren't being understood by Vivado, since the ports ended up unconnected and some have the wrong IO standard (see screenshots). I would upload the project file, but it looks like its too big for the forum by a few MBs, so I posted some screenshots instead, as well as the board files. Does anyone know what could be wrong? I know a UCF file with LOC constraints will work, but that defeats the whole point of the board files that include pin definitions. mig.prj board.xml part0_pins.xml preset.xml
  9. Hello, I'm currently trying to implement a simple low-pass filter using the FIR Compiler available in the IP catalog. My design is very basic, I've generated a sine wave using the DDS IP : * Configuration Options : Phase generator and SIN COS LUT * System clock : 100 MHz * Mode of operation : Standard * Output frequency : 1.2 MHz * Output width : 8 Bits I want now to apply a low-pass filter and to see how is it going in simulation, using Analog waveform style. To generate the coefficients, I am using Matlab and the filterDesigner. Here are the specifications : * Lowpass, FIR (Equiripple) * Fs : 2.7 MHz * Fpass : 1.3 MHz * Fstop : 1.35 MHz * Apass : 1 dB * Astop :40 dB Then, I generate a .COE file which I use in the FIR compiler. I specify these options : * Filter type : Single rate * Input sampling frequency : 2.7 MHz * Clock frequency : 100 MHz * Coefficient type : signed, on 16 bits * Coefficient structure : Inferred * Input data type : Signed, on 8 bits * Output rounding mode : Full precision The screenshot shows what I obtain and it seems that it is not working very well. Does anybody can explain me what is going on ? Do I make some mistakes when I am setting up the filter ? Thank you very much for your help !
  10. I bought a Spartan-3E 500K Starter Board from ebay. The board looks new to me. When I plugged in the power supply, only 1 (red or power) of 3 LEDs (red, yellow and green) was on. The remaining 2 LEDs were off. In addition, there was no display on LCD. What's going on with my board? Is it a bad board?
  11. Hi, I'm using a nexys 3 sparten 6 fpga . I need to interface it with a keyboard, is there any core available to do that?
  12. Hello. I'm new to Verilog and I was assigned to code a servo controller in Verilog. The system clock runs at 50MHz. The period of the servo is 20ms, the minimum pulse width is 0.6ms (at 0 degrees), at 1.5ms for 90 degrees, and 2.4ms for 180 degrees. When the user presses one of the buttons on the FPGA and the button corresponds to increment, the servo has to move 5 degrees clockwise. If the user presses the button corresponding to decrement, the servo has to move 5 degrees counterclockwise. Please help me. I looked online for resources but I don't seem to understand them. Thank you so much in advance!
  13. sachin

    ethernet mac

    Hi, Can i have tutorial for bulding ethernet mac in nexys 3 board
  14. I want to store the image matrix into block RAM.In my UART receiver code I have instantiated BRAM module for writing purpose.Is this way is correct? Wheneve Instantiate there is not declring error.Where can I ear functionality of Block RAM
  15. Hello ! I'm currently encoutering an issue about how to assign each digit of a number on the seven segment display. For example, if I have the number 1932, how to affect the '2' on the first digit display . The '3' on the second, the '9' on the third, etc... Actually, I have a 4-bit BCD (which functions) and I want to display the decimal number. My output, bcd0, bcd1, bcd2, bcd3 represents the ones, the tens, the hundres and the thousands). I'm decoding each output like that : case bcd0 is when "0000"=> seven_seg<="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd1 is when "0000"=> seven_seg<="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd2 is when "0000"=> seven_seg <="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd3 is when "0000"=> seven_seg <="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; Of course, I know that I have to activate the 4 first anodes (low level). And that I have to assign each bit of "seven_seg" to the good pin on the .XCF file. Thank you very much for help !
  16. Dear Digilent Team, I have just reprogrammed the ft2232h eeprom in the FT_PROG. Now the Vivado says: "There is no current hw_target." So it looks that I were destroyed the EEPROM code in the nexys video. Could You send me a program to fix this issue ? Thank You. andrewna
  17. Hello! I'm currently working on a project and i need to use differential signaling. I'm using Arty development platform (designed around the Artix-7™ FPGA) and I have some problems in generating the two differential signals (P and N). I used an oscilloscope to check the signal that I want to be sent (MDO) by configuring it as a single ended signal and it is correct. But when I use OBUFDS the two differential signals are logic low all time. I put the verilog code below and the .xdc file configuration. Thank you very much! Have a good day! OBUFDS #( .IOSTANDARD("TMDS_33"), // Specify the output I/O standard .SLEW("FAST") // Specify the output slew rate ) OBUFDS_inst ( .O(ME_DIFF_P), // Diff_p output .OB(ME_DIFF_N), // Diff_n output .I(MDO) // Buffer input ); # .xdc file set_property PACKAGE_PIN U12 [get_ports ME_DIFF_P] set_property PACKAGE_PIN V12 [get_ports ME_DIFF_N] set_property IOSTANDARD TMDS_33 [get_ports ME_DIFF_P] set_property IOSTANDARD TMDS_33 [get_ports ME_DIFF_N] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_switching_activity -deassert_resets
  18. Hi, I am working on a unit that has Spartan 6 XC6SLX9 (TGFP144) devices. Each board has 1 Spartan 6 on it and each board is just a copy of the other (briefly, the unit is a 4 channel transmitter and I have each board handling 1 channel - so they are identical copies). I'm trying to find the best way to program these boards in the field remotely (so I can't rely on removing / attaching cables, pushing buttons etc.) One possible solution is to use this: http://store.digilentinc.com/jtag-smt2-nc-surface-mount-programming-module/ on my motherboard and daisy chain JTAG lines as per Xilinx docs. QUESTION: Can I use the JTAG-SMT2-NC with a full speed USB port (as opposed to a high speed USB port)? The USB hub we use on our motherboard is full speed only. I am not looking for any specific JTAG programming speeds. Second solution I have is to have an SPI flash for each FPGA and have them all on the same "shared" bus (the SPI flashes would be programmed by my uC on the motherboard). Since the FPGAs take control of the SPI bus on configuration, I'd be "de-coupling" the "shared" bus from the per-board bus with a buffer as shown below: http://imgur.com/a/jpsjx So when PROGRAM_B is raised to HIGH, the buffer tri-states its outputs (so the shared bus from other FPGAs is no longer in contention). QUESTION: Thoughts? Does this seem reasonable? I'm slightly leaning towards the first option - it seems more robust since JTAG was made to do the daisy chaining stuff -- but depends on whether full speed will work. Thanks, Aditya
  19. Hi, I'm new to FPGAs, so I purchased a BASYS3 to play around with. In following the "Getting Started with BASYS 3" video (youtube), I cannot save e a configuration to a memory device as that option is grayed out in my case (see attached screen capture). Does anyone have any ideas what's causing this and how to overcome it? Thanks in advance
  20. Hi, I tried to learn RS232 and created a project on Basys 3 with Pmod R232. The plan I would like to do is that whenever I set binary number at 8 switches on Basys 3, the data will be passed to the PC and I can see the character in the hyperterminal. At the same time, the LEDs for the "ON" switches with be turned on. I have successfully generated the bitstream file but it doesn't seems function. Include the Verilog code for transmitter, receiver and top modules. It will be great if someone can give hints to let me finish this project. P.S. I have used the logic from http://www.ece301.com/ Transmitter module transmitter( input clk, //clock input reset, // reset input transmit, //input to say transmission is ready, can be push button or switch input [7:0] data, // data transmitted output reg TxD // transmit data line ); reg TxDready; //register variable to tell when transmission is ready reg [3:0] bitcounter; //vector 4 bits counter to count up to 9 reg [13:0] counter; //vector 14 bits counter to count the baud rate, counter = clock / baud rate reg state, nextstate; // register state variable reg [9:0] rightshiftreg; // vector data needed to be transmitted 1 start, 8 data & 1 stop bit reg shift, load, clear; //register variable for shifting, loading the bits and clear the counter //counter logic always @ (posedge clk) //positive edge begin if (reset) begin // reset is asserted (reset = 1) state <=0; // state is idle (state = 0) counter <=0; // counter for baud rate is reset to 0 bitcounter <=0; //counter for bit transmission is reset to 0 end else begin counter <= counter + 1; //start counting if (counter >= 10415) //if count to 5207 because we start the conunt from 0, so not 5208 begin state <= nextstate; //state change to next state counter <=0; // reset counter to 0 if (load) rightshiftreg <= {1'b1,data,1'b0}; //load the data if load is asserted if (clear) bitcounter <=0; // reset the bitcounter if clear is asserted if (shift) begin // if shift is asserted rightshiftreg <= rightshiftreg >> 1; //right shift the data as we transmit the data from lsb bitcounter <= bitcounter + 1; //count the bitcounter end end end end //state machine always @ (state, bitcounter, transmit,rightshiftreg) //trigger by change of state, bitcounter or transmit begin load <=0; // set load equal to 0 at the beginning shift <=0; // set shift equal to 0 at the beginning clear <=0; // set clear equal to 0 at the beginning TxDready <=1; // set TxDReady equal to 1 so no transmission. When TxD is zero, the receiver knows it is transmitting TxD <=0; // set TxD equals to 0 at the beginning to avoid latch case (state) 0: begin // idle state if (transmit) begin // assert transmit input nextstate <=1; // set nextstate register variable to 1 to transmit state load <=1; // set load to 1 to prepare to load the data shift <=0; // set shift to 0 so no shift ready yet clear <=0; // set clear to 0 to avoid clear any counter end else begin // if transmit not asserted nextstate <=0; // next state is 0 back to idle TxDready <=1; // set TxD to 1 to avoid any transmission end end 1: begin // transmit state if (bitcounter >=9) begin // check if transmission is complete or not. If complete nextstate <= 0; // set nextstate back to 0 to idle state clear <=1; // set clear to 1 to clear all counters end else begin // if transmisssion is not complete nextstate <= 1; // set nextstate to 1 to stay in transmit state shift <=1; // set shift to 1 to continue shifting the data TxD <= rightshiftreg[0]; // shift the bit to output TxD end end default: begin // idle state if (transmit) begin // assert transmit input nextstate <=1; // set nextstate register variable to 1 to transmit state load <=1; // set load to 1 to prepare to load the data shift <=0; // set shift to 0 so no shift ready yet clear <=0; // set clear to 0 to avoid clear any counter end else begin // if transmit not asserted nextstate <=0; // next state is 0 back to idle TxDready <=1; // set TxD to 1 to avoid any transmission end end endcase end endmodule Receiver module receiver( input clk, //input clock input reset, //input reset input RxD, //input receving data line output [7:0]RxData // output for 8 bits data // output [7:0]LED // output 8 LEDs ); reg shift; // register variable shift to trigger shifting data reg state, nextstate; // register state variable reg [3:0] bitcounter; // register vector 4 bits counter to count up to 9 reg [3:0] samplecounter; // register vector 4 bits sample counter to count up to 9 reg [13:0] counter; // register vector 14 bits counter to count the baud rate reg [9:0] rxshiftreg; //register vector for bit shifting reg clear_bitcounter,inc_bitcounter,inc_samplecounter,clear_samplecounter; //register variable to clear or increment the counter assign RxData = rxshiftreg [8:1]; // assign the RxData // assign LED = RxData; // assign the LED output //counter logic always @ (posedge clk) begin if (reset)begin // if reset is asserted state <=0; // set state to idle bitcounter <=0; // reset the bit counter counter <=0; // reset the counter samplecounter <=0; // reset the sample counter end else begin // if reset is not asserted counter <= counter +1; // start count in the counter if (counter >= 3472) begin // if counter reach the baud rate with sampling counter <=0; //reset the counter state <= nextstate; // assign the state to nextstate if (shift)rxshiftreg <= {RxD,rxshiftreg[9:1]}; //if shift asserted, load the receiving data if (clear_samplecounter) samplecounter <=0; // if clear sampl counter asserted, reset sample counter if (inc_samplecounter) samplecounter <= samplecounter +1; //if increment counter asserted, start sample count if (clear_bitcounter) bitcounter <=0; // if clear bit counter asserted, reset bit counter if (inc_bitcounter)bitcounter <= bitcounter +1; // if increment bit counter asserted, start count bit counter end end end //state machine always @ (state or RxD or bitcounter or samplecounter or rxshiftreg) // triggered by change of state, Rxd and bit counter begin shift <= 0; // set shift to 0 to avoid any shifting clear_samplecounter <=0; // set clear sample counter to 0 to avoid reset inc_samplecounter <=0; // set increment sample counter to 0 to avoid any increment clear_bitcounter <=0; // set clear bit counter to 0 to avoid claring inc_bitcounter <=0; // set increment bit counter to avoid any count nextstate <=0; // set nextstate equals to 0 at the beginning to avoid any latch case (state) 0: begin // idle state if (RxD) // if input RxD data line asserted nextstate <=0; // back to idle state because RxD needs to be low to start transmission else begin // if input RxD data line is not asserted nextstate <=1; //jump to receiving state clear_bitcounter <=1; // trigger to clear bit counter clear_samplecounter <=1; // trigger to clear sample counter end end 1: begin // receiving state if (samplecounter==1) shift <=1; // if sample counter is 1, trigger shift if (samplecounter==3) begin // if sample counter is 3 as the sample rate used is 3 if (bitcounter ==9) begin // check if bit counter if 9 or not nextstate <= 0; // back to idle state if bit counter is 9 as receving is complete end inc_bitcounter <=1; // trigger the increment bit counter if bit counter is not 9 clear_samplecounter <=1; //trigger the sample counter to reset the sample counter end else inc_samplecounter <=1; // if sample is not equal to 3, keep counting end default: begin // idle state if (RxD) // if input RxD data line asserted nextstate <=0; // back to idle state because RxD needs to be low to start transmission else begin // if input RxD data line is not asserted nextstate <=1; //jump to receiving state clear_bitcounter <=1; // trigger to clear bit counter clear_samplecounter <=1; // trigger to clear sample counter end end endcase end endmodule Top module top( input btn0, input [8:0] sw, // input 8 switches , one for transmit input clk, input RxD, output TxD, output [7:0]LED // output 8 LEDs ); wire [7:0] data; assign data = sw; receiver R1 (.clk(clk), .reset(btn0), .RxD(RxD), .RxData(LED)); transmitter T1 (.clk(clk),.transmit(sw[8]), .reset(btn0),.data(sw[7:0]), .TxD(TxD)); endmodule
  21. Hi, I am using Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit and I am newbie for using this board. I'm following this link to generate an interrupt using GPIO switches and turn off a led : http://www.wiki.xilinx.com/Linux+GPIO+Driver. The drivers works correctly and the led is heartbeating, when i check /proc/interrupts i get: ... 223: 0 0 0 0 GICv2 154 Level fd4c0000.dma 224: 0 0 0 0 xgpio 0 Edge sw14 233: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 ... but when i switch on cpu stops and i get this error: [email protected]_1:~# [ 18.111391] Unable to handle kernel paging request at virtual address b9410a80aa13043f [ 18.119243] pgd = ffffffc87ad07000 [ 18.122615] [b9410a80aa13043f] *pgd=0000000000000000, *pud=0000000000000000 [ 18.129559] Internal error: Oops: 96000004 [#1] SMP [ 18.134420] Modules linked in: [ 18.137460] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.4.0 #78 [ 18.143361] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.148136] task: ffffffc00224efc0 ti: ffffffc002240000 task.ti: ffffffc002240000 [ 18.155613] PC is at xgpio_irqhandler+0x2c/0x144 [ 18.160202] LR is at xgpio_irqhandler+0x1c/0x144 [ 18.164801] pc : [<ffffffc0003c8ee0>] lr : [<ffffffc0003c8ed0>] pstate: 600001c5 [ 18.172185] sp : ffffffc002243d00 [ 18.175476] x29: ffffffc002243d00 x28: 0000000000000000 [ 18.180769] x27: 0000000000000000 x26: ffffffc0022c2000 [ 18.186063] x25: ffffffc00078acf0 x24: ffffff8000015000 [ 18.191358] x23: ffffffc0003c8eb4 x22: b9410a80aa1303f7 [ 18.196653] x21: 0000000000000000 x20: 0000000000000000 [ 18.201948] x19: ffffffc002227000 x18: 0000000000000001 [ 18.207242] x17: 0000000000000006 x16: ffffffbe1dae9f68 [ 18.212537] x15: ffffffc87b08f000 x14: 0000000000000007 [ 18.217832] x13: ffffffc87b801128 x12: 0000004000000000 [ 18.223127] x11: ffffffc002246000 x10: 00000000000006e0 [ 18.228422] x9 : ffffffc002243e70 x8 : ffffffc87b400058 [ 18.233716] x7 : ffffffc87b400d88 x6 : 0000000000000002 [ 18.239011] x5 : 00000000fffffffa x4 : ffffffc87b400d89 [ 18.244306] x3 : 0000000000000000 x2 : 0000000000000000 [ 18.249601] x1 : 0000000000000020 x0 : 0000000000000000 [ 18.254895] [ 18.256373] Process swapper/0 (pid: 0, stack limit = 0xffffffc002240020) [ 18.263060] Stack: (0xffffffc002243d00 to 0xffffffc002244000) [ 18.268790] 3d00: ffffffc002243d50 ffffffc0000d1088 ffffffc002227000 0000000000000000 [ 18.276609] 3d20: 0000000000000000 ffffffc002249040 ffffff8000014010 ffffffc0000d13cc [ 18.284421] 3d40: ffffffc002243d50 ffffffc0000d107c ffffffc002243d60 ffffffc0000d13a0 [ 18.292232] 3d60: ffffffc002243da0 ffffffc000080cec ffffff800001400c ffffffc002279000 [ 18.300045] 3d80: ffffffc002243de0 ffffffc0000e5ed0 ffffffc87b808000 00000079000ec410 [ 18.307857] 3da0: ffffffc002243f00 ffffffc000083da8 ffffffc002240000 ffffffc002246000 [ 18.315668] 3dc0: ffffffc002243f00 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.323480] 3de0: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.331292] 3e00: 0000000000000000 000000001999999a 002aad4b00000000 00000000fffeecaa [ 18.339104] 3e20: 00000000fffeecab ffffffc002243e70 00000000000006e0 ffffffc002246000 [ 18.346916] 3e40: 0000004000000000 ffffffc87b801128 0000000000000007 ffffffc87b08f000 [ 18.354729] 3e60: ffffffbe1dae9f68 0000000000000006 0000000000000001 ffffffc002240000 [ 18.362541] 3e80: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc002243f20 [ 18.370352] 3ea0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.378164] 3ec0: 0000000000000000 ffffffc002243f00 ffffffc000084e6c ffffffc002243f00 [ 18.385977] 3ee0: ffffffc000084e70 0000000060000145 ffffffc00078acf0 ffffffc00077c278 [ 18.393789] 3f00: ffffffc002243f10 ffffffc0000ca2e0 ffffffc002243f20 ffffffc0000ca418 [ 18.401600] 3f20: ffffffc002243f90 ffffffc000779080 ffffffc0022c5000 ffffffc0022c5000 [ 18.409413] 3f40: ffffffc0022c5000 ffffffc002246000 ffffffc87ffa2580 ffffffc000a6fca8 [ 18.417224] 3f60: 000000000231c000 000000000231f000 ffffffc0000801d8 0000000000000000 [ 18.425037] 3f80: ffffffc002243f90 ffffffc000779078 ffffffc002243fa0 ffffffc000a3d94c [ 18.432848] 3fa0: 0000000000000000 0000000000780000 0000000000000000 0000000000000e12 [ 18.440660] 3fc0: 0000000004080000 0000000000000000 0000000000000000 0000000000000000 [ 18.448472] 3fe0: 0000000000000000 ffffffc000a6fca8 0000000000000000 0000000000000000 [ 18.456281] Call trace: [ 18.458707] [<ffffffc0003c8ee0>] xgpio_irqhandler+0x2c/0x144 [ 18.464353] [<ffffffc0000d1088>] generic_handle_irq+0x24/0x38 [ 18.470079] [<ffffffc0000d13a0>] __handle_domain_irq+0x60/0xac [ 18.475895] [<ffffffc000080cec>] gic_handle_irq+0x60/0xb4 [ 18.481274] Exception stack(0xffffffc002243db0 to 0xffffffc002243ed0) [ 18.487699] 3da0: ffffffc002240000 ffffffc002246000 [ 18.495518] 3dc0: ffffffc002243f00 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.503329] 3de0: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.511142] 3e00: 0000000000000000 000000001999999a 002aad4b00000000 00000000fffeecaa [ 18.518954] 3e20: 00000000fffeecab ffffffc002243e70 00000000000006e0 ffffffc002246000 [ 18.526766] 3e40: 0000004000000000 ffffffc87b801128 0000000000000007 ffffffc87b08f000 [ 18.534578] 3e60: ffffffbe1dae9f68 0000000000000006 0000000000000001 ffffffc002240000 [ 18.542390] 3e80: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc002243f20 [ 18.550202] 3ea0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.558013] 3ec0: 0000000000000000 ffffffc002243f00 [ 18.562868] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 18.567643] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 18.573284] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 18.579101] [<ffffffc000779080>] rest_init+0x74/0x7c [ 18.584049] [<ffffffc000a3d94c>] start_kernel+0x394/0x3a8 [ 18.589427] [<0000000000780000>] 0x780000 [ 18.593421] Code: b4000820 f9400800 f9400414 f9401ef6 (f94026c0) [ 18.599503] ---[ end trace fc72e20977be1640 ]--- [ 18.604096] Kernel panic - not syncing: Fatal exception in interrupt [ 18.610435] CPU3: stopping [ 18.613125] CPU: 3 PID: 0 Comm: swapper/3 Tainted: G D 4.4.0 #78 [ 18.620241] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.625013] Call trace: [ 18.627447] [<ffffffc000087da8>] dump_backtrace+0x0/0x114 [ 18.632829] [<ffffffc000087ed0>] show_stack+0x14/0x1c [ 18.637865] [<ffffffc000393cf8>] dump_stack+0x84/0xa0 [ 18.642897] [<ffffffc00008d4cc>] handle_IPI+0x18c/0x1a0 [ 18.648104] [<ffffffc000080d28>] gic_handle_irq+0x9c/0xb4 [ 18.653486] Exception stack(0xffffffc87b8efdf0 to 0xffffffc87b8eff10) [ 18.659910] fde0: ffffffc87b8ec000 ffffffc002246000 [ 18.667730] fe00: ffffffc87b8eff40 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.675541] fe20: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.683353] fe40: 0000000000000000 000000001999999a 000a037a00000000 00000000fffeed1b [ 18.691165] fe60: 00000000fffeed1c ffffffc87b8efeb0 00000000000006e0 0000000000000005 [ 18.698977] fe80: ffffffc00078b5d4 ffffffc073ad7b80 ffffffc87b325380 ffffffc87ba30000 [ 18.706789] fea0: ffffffbe1db0baa0 0000000000000006 0000000000000001 ffffffc87b8ec000 [ 18.714601] fec0: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc87b8eff60 [ 18.722413] fee0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.730224] ff00: 0000000000000000 ffffffc87b8eff40 [ 18.735078] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 18.739853] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 18.745496] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 18.751310] [<ffffffc00008cfcc>] secondary_start_kernel+0x11c/0x140 [ 18.757559] [<000000000008103c>] 0x8103c [ 18.761464] CPU2: stopping [ 18.764157] CPU: 2 PID: 0 Comm: swapper/2 Tainted: G D 4.4.0 #78 [ 18.771273] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.776045] Call trace: [ 18.778479] [<ffffffc000087da8>] dump_backtrace+0x0/0x114 [ 18.783861] [<ffffffc000087ed0>] show_stack+0x14/0x1c [ 18.788895] [<ffffffc000393cf8>] dump_stack+0x84/0xa0 [ 18.793929] [<ffffffc00008d4cc>] handle_IPI+0x18c/0x1a0 [ 18.799136] [<ffffffc000080d28>] gic_handle_irq+0x9c/0xb4 [ 18.804518] Exception stack(0xffffffc87b8ebdf0 to 0xffffffc87b8ebf10) [ 18.810942] bde0: ffffffc87b8e8000 ffffffc002246000 [ 18.818762] be00: ffffffc87b8ebf40 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.826573] be20: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.834385] be40: 0000000000000000 000000001999999a 000f424000000000 00000000fffeed31 [ 18.842197] be60: 00000000fffeed32 ffffffc87b8ebeb0 00000000000006e0 ffffffc002246000 [ 18.850009] be80: 0000004000000000 ffffffc87b801128 000000000000001c ffffffc87ac9c000 [ 18.857821] bea0: ffffffbe1dadc240 0000000000000006 0000000000000001 ffffffc87b8e8000 [ 18.865633] bec0: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc87b8ebf60 [ 18.873445] bee0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.881256] bf00: 0000000000000000 ffffffc87b8ebf40 [ 18.886110] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 18.890885] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 18.896527] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 18.902342] [<ffffffc00008cfcc>] secondary_start_kernel+0x11c/0x140 [ 18.908591] [<000000000008103c>] 0x8103c [ 18.912496] CPU1: stopping [ 18.915188] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G D 4.4.0 #78 [ 18.922305] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.927077] Call trace: [ 18.929511] [<ffffffc000087da8>] dump_backtrace+0x0/0x114 [ 18.934893] [<ffffffc000087ed0>] show_stack+0x14/0x1c [ 18.939927] [<ffffffc000393cf8>] dump_stack+0x84/0xa0 [ 18.944961] [<ffffffc00008d4cc>] handle_IPI+0x18c/0x1a0 [ 18.950168] [<ffffffc000080d28>] gic_handle_irq+0x9c/0xb4 [ 18.955550] Exception stack(0xffffffc87b8e3df0 to 0xffffffc87b8e3f10) [ 18.961974] 3de0: ffffffc87b8e0000 ffffffc002246000 [ 18.969794] 3e00: ffffffc87b8e3f40 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.977605] 3e20: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.985417] 3e40: 0000000000000000 000000001999999a 000cdfe600000000 00000000fffeed27 [ 18.993229] 3e60: 00000000fffeed28 ffffffc87b8e3eb0 00000000000006e0 ffffffc002246000 [ 19.001041] 3e80: 0000004000000000 ffffffc87b801128 000000000000000e ffffffc87b3de000 [ 19.008853] 3ea0: ffffffbe1daf58b0 0000000000000006 0000000000000001 ffffffc87b8e0000 [ 19.016665] 3ec0: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc87b8e3f60 [ 19.024477] 3ee0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 19.032288] 3f00: 0000000000000000 ffffffc87b8e3f40 [ 19.037142] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 19.041917] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 19.047559] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 19.053374] [<ffffffc00008cfcc>] secondary_start_kernel+0x11c/0x140 [ 19.059623] [<000000000008103c>] 0x8103c [ 19.063529] ---[ end Kernel panic - not syncing: Fatal exception in interrupt This is my pl.dtsi: / { amba_pl: amba_pl { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges ; axi_gpio_0: [email protected] { #gpio-cells = <2>; #interrupt-cells = <2>; compatible = "xlnx,xps-gpio-1.00.a"; gpio-controller ; interrupt-controller ; interrupt-parent = <&gic>; interrupts = <0 89 1>; reg = <0x0 0x80000000 0x0 0x10000>; xlnx,all-inputs = <0x1>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x0>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x00000000>; xlnx,dout-default-2 = <0x00000000>; xlnx,gpio-width = <0x8>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x1>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xFFFFFFFF>; xlnx,tri-default-2 = <0xFFFFFFFF>; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw14 { label = "sw14"; gpios = <&axi_gpio_0 0 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; axi_gpio_1: [email protected] { #gpio-cells = <2>; compatible = "xlnx,xps-gpio-1.00.a"; gpio-controller ; reg = <0x0 0x80010000 0x0 0x10000>; xlnx,all-inputs = <0x0>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x1>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x00000000>; xlnx,dout-default-2 = <0x00000000>; xlnx,gpio-width = <0x8>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x0>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xFFFFFFFF>; xlnx,tri-default-2 = <0xFFFFFFFF>; }; gpio-leds { compatible = "gpio-leds"; led-ds23 { label = "led-ds23"; gpios = <&axi_gpio_1 0 0>; default-state = "on"; linux,default-trigger = "heartbeat"; }; }; }; };
  22. Good Day, I looked on the forum to see if this question was answered. While I saw hints to the answer, it wasn't clear. If this is a repeat, my apologies. I just purchased one of the Anvyl boards during the end of year sale. While I have ISE and Vivado both installed, I generally use Vivado only now for my Nexys4 DDR and ZedBoard, If possible, I'd like to use Vivado for designs on the Anvyl. Is this possible? If so, are their any Vivado board files available for this board (I searched but couldn't find any), or is it just a matter of me configuring the right FPGA and converting the info in the UCF file to a set of Vivado constraints? Thanks, Dave
  23. Hello! My task is creation of real-time system which can draw simple graphics figure on monitor (VGA) when the system register input pulse. The main difficulty is to draw this image only once (for measuring man's reaction time: time between image drawing and the button pressing). I think it'll possible to use FPGA to register input pulse and to generate VGA signal with required parameters. But I don't undestand can the ONLY ONE image frame be drawn at input pulse interrupting or not? The main task is to minimize time delays and in this case I can't use the standart solutions. For example, using Raspberry Pi or a similar device is accompanied by the necessary of screen refreshing and image drawing binding. This adds a random time delay from 0ms (if the screen refresh time coincides with time of input external pulse which starts drawing figures) to 1/60Hz=16.7ms. I need your advices or suggestions. Thanks!
  24. Hi. I want to generate 15MHz clock from 40MHz system clock. I could use DCM to generate this clock but i want to use counter for that purpose. Can someone tell me that how can i do that?