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Found 313 results

  1. bakytzhan

    Divide a clock signal

    Hello everybody! Guys, I wanted to ask How to do a seconds, minutes signal with Basys 3 ? How can I delay a 100 Mhz clock?
  2. Hi. I'm new to programming FPGAs. I just would like to ask, what are the recommended FPGA boards for beginners? My university currently uses the Spartan 3E Starter Board but from the reviews that I've read, the Spartan 3E is quite old already and some say that I should consider buying other FPGA boards that have more functionalities and processing power.
  3. I have an Arty board and USBUART Pmod card. I want to send data from Windows to FPGA on Arty via USBUART Pmod. First, can this be done, and how? Is there ref. design? Thanks.
  4. aysekban

    Basys3, TW-131

    Hi, I have an TW-131 coin acceptor. That has three cables, one is connected to 12V, one is ground and one is for the pulse. When money is inserted the white cable gives a pulse for 50ms. I am not sure how to connect this coin acceptor to BASYS3 board. I mean to which part of the BASYS3 do I need to connect the white cable. Also I am not sure about how to write a code that gives an output "1" when money inserted to con acceptor and "0" when no money is inserted. Can you help me?
  5. Hi. I want to interface EEPROM with the FPGA. Can someone tell me that what is the general size of EEPROM to be attach with Virtex 4 FPGA? Thanks
  6. HI guys ; please i want a some help; i want to connect Nexys 4 board with RTLSDR receiver and get data from him and do processing in FPGA , some people tell me it is hard with VHDL and they propose to do this with microblaze , i need some help to do this , (advices , tutorial ....). thanks
  7. Hello, I have ordered the Artix-7 35T "Arty" FPGA Evaluation Kit to educate FPGA design (VHDL) using Vivado tool. Today, I am looking for some starting points: tutorials, websites, books, online courses, ... All help & tips are welcome. Thanks. JrV
  8. Hi, i need to change the eeprom a little to achieve my communication tasks I need the whole file(firmware source program) in order to understand it and achieve my needs by using it. who can help me! Thank you very much!
  9. Hi, i need to change the eeprom a little to achieve my communication tasks I need the whole file(firmware source program) in order to understand it and achieve my needs by using it. Thank you very much!
  10. I want to build an Audio Processor using Diligent Atlys. I want to know whether is it practically realizable??? I don't have dedicated faculty in my college due to which i will require help . Has anyone done it in the past so that he or she could help me or guide me if i could get stuck???
  11. Hi, i broken the eeprom IC5 where the Cypress CY7C68013A firmware is stored. I need the .iic file in order to upload it again to a new eeprom with Cypress CyConsole tool. Thank you very much!
  12. Hi, i broken the eeprom where the Cypress CY7C68013A firmware is stored.(Nexys2) I need the .iic file in order to upload it again to a new eeprom with Cypress CyConsole tool. Thank you very much!
  13. Hello I need advice on which FPGA board to select for a camera project I'm working on. This is the first time I have considered using an FPGA so my knowledge is limited. Any general advice about first use of FPGAs would also be appreciated. It needs the following main features and capabilities. 1. It needs to be able to interface with the image sensor which uses 1.8v logic. I read somewhere that different voltages can be used for certain sections of some FPGAs which would be very useful in this case. 2. SDRAM as a temporary store for captured images. I see that some boards already have this. 3. Mirco SD card slot, for permanent storage of multiple captured images.
  14. Hi members, We plan to implement an interface to communicate among multiple FPGAs(now we will use Zybo). The interface is required fast communication speed(10GB/sec -). We don't know how to do it. Please let us know how to implement it, your supported products around zybo or any other information. Best regards,
  15. Hi to all! I'm trying to make a pocket calculator using a FPGA. The numbers are entered from a PS2 keyboard and displayed on a 16x2 LCD. Operations like: +, -, / , * are made by a 32bit floating point ALU. How can i convert fractional part into decimal from the result : ex- 1101.11 = 13.75 for the int part i'm using this algorithm https://en.wikipedia.org/wiki/Double_dabble but for fractional ?????????
  16. Hello all, I am writing C code for the arty board to basically emulate the automotive SENT protocol. I just need to know if the output pins are open drain on this board to prevent accidental loads that could damage my parts. Let me know if any further information is required. Thanks, Tim
  17. Hi all, I am using a Nexys 4 DDR board to interface microSD and microSDHC cards using the SPI mode. (For those interested in what the whole thing is all about, click here.) Might it be, that microSD cards are needing current in the range of 10mA (e.g. look at Transcend's 2GB SD card datasheet - link) and microSDHC (SDHC vs SD) are needing 10x of this, e.g. look here at Samsung's 32GB SDHC card: http://www.singerphoto.co.za/SingerPhotographicOnlineDocuments/WebImages/SellSheetPDFs/mesamp64a.pdf How much current is the Nexys 4 DDR SD Card slot able to supply? The first card I wrote about above (Transcend's 2GB SD V2 card) works fine with my controller, the second card (Samsung's) is not even initializing (no response to CMD0). (Some other SDHC cards are working with my controller, see below.) Are there some settings I need to do in the UCF file, e.g. fast SLEW rate or another value for DRIVE (to supply more current)? Currently my UCF file looks like this: ##Micro SD Connector NET "SD_RESET" LOC = E2 | IOSTANDARD = LVCMOS33; NET "SD_CLK" LOC = B1 | IOSTANDARD = LVCMOS33; NET "SD_MOSI" LOC = C1 | IOSTANDARD = LVCMOS33; NET "SD_MISO" LOC = C2 | IOSTANDARD = LVCMOS33 | PULLUP; Here is the source (Link) of my controller. I tested it with ~40 cards. 20 of them are SD cards Version 1 and Version 2 (from 64 MB up to two GB): Works fine and stable with all of them. 20 of them are SDHC. When it comes to SDHC, it works with about 50% of the cards (well - works kind of: I need to reset after each read command). The other 50% are showing really strange behaviours: Some are only reporting themselves as a SDHC during the coldstart/hard reset (insert card) and from then on "claim" to be a SD V2 card, others are initializing well but when it comes to reading, they never send a R1 on READ_BLOCK, etc. While googling I found some comments in forums, that strange behaviour might be rooted in a lack of current, so this is the background of my question. Best regards Mirko
  18. Hi, I have problems with my counter. Sorry for my poor english Register should be reset on the posedge of signal x1 and should be increased on the posedge of CLOCK. I know that register can be changed only in one always process, but I don't know how do that. The error is: Line 33: Signal register[11] in unit blagam_o_synteze is connected to following multiple drivers: blagam_o_synteze.v
  19. Dr. Lizy Kurian John from University of Texas at Austin shared the lab manual for EE 460 Digital Systems using Verilog at http://users.ece.utexas.edu/~ljohn/teaching/ee460m_lab_manual.pdf
  20. Professors and researchers from University of Houston make use of Zedboard and Xilinx Vivado High Level Synthesisto implement the data encryption in the cloud computing. They explained this concept in two different conferences Field Programmable Logic (FPL) 2014 - Privacy Preserving Large Scale DNA Read-mapping in MapReduce Framework using FPGAs http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6927414 IEEE Cloud 2014 - PFC: Privacy Preserving FPGA Cloud - a Case Study of MapReduce http://ieeexplore.ieee.org/xpl/login.jsp?tp=&arnumber=6973752&url=http%3A%2F%2Fieeexplore.ieee.org%2Fiel7%2F6968679%2F6973706%2F06973752.pdf%3Farnumber%3D6973752 The project is also sponsored by NATO. http://www.uh.edu/news-events/stories/2016/March/032316ShiNATO
  21. Although this isn't using a Digilent FPGA board, here is how to drive a low-cost stepper motor and to count the steps taken. It is using a 5V stepper motor, but if you have 12V motor & driver board it may also work for you. http://hamsterworks.co.nz/mediawiki/index.php/Stepper
  22. Hello everyone, I am using a Nexys 4 DDR for a school project. I am building a system that uses a video camera to detect and track human motion. Several questions: 1. Which port should I use to connect the camera? The immediate one available on the board is the USB host connector, but is it possible to use it to connect a camera? 2. Are there any PMODs available to connect a camera module? 3. Any recommendations for a specific camera model to use for this project? Basically, I need to take the video input, perform some filtering to recognize face and arms, downsample the video and store it in a memory buffer, and output the video real-time to a VGA monitor. Thanks!
  23. Vonmuller

    Working with Pmod DA4

    Good morning, I'm trying to program Pmod DA4, connected to Nexys 4 DDR, using VHDL. As refernce voltage I'm using the internal reference and the maximum output should be 5V, according to the AD5628 datasheet. However, my maximum output voltage doesn't exceed 2.5V. I wonder if I'm doing anything wrong or there is actually a AD5628-1 modification is used in Pmod DA4, that allows only 2.5V as the maximum output? How can I figure out what modification of AD5628 is used in Pmod DA4? Thank you in advance. Best regards, Alex dig2an.vhd
  24. Hi: I would like to implement an application in my fpga to communicate to the PC. I don't want to use the SDK, I prefer VHDL. So, I can generate a Xilinx LogiCORE Tri-Mode Ethernet MAC using Xilinx's Coregen, but I don't know how to connect it. For example, the global clock is 125Mhz, and the atlys only provides me a 100Mhz. Should I use a clock generator? Thanks.
  25. I've been beavering away on a large project, but ended up thinking about how small a Serial TX module could be. While out splitting firewood stumbled over the idea that takes it down top 12 LUTs and 11 flip-flops library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity tiny_rs232_tx is Port ( clk : in STD_LOGIC; bit_tick : in STD_LOGIC; data : in STD_LOGIC_VECTOR(7 downto 0); data_enable : in STD_LOGIC; tx : out STD_LOGIC := '1'; busy : out STD_LOGIC ); end tiny_rs232_tx; architecture Behavioral of tiny_rs232_tx is signal shift_reg : std_logic_vector(9 downto 0) := (others => '1'); signal i_busy : std_logic; begin busy <= i_busy; with shift_reg select i_busy <= '0' when "0000000000", '1' when others; clk_proc: process(clk) begin if rising_edge(clk) then if i_busy = '0' and data_enable = '1' then shift_reg <= '1' & data & '0'; end if; if bit_tick = '1' then if i_busy = '1' then tx <= shift_reg(0); shift_reg <= '0' & shift_reg(9 downto 1); end if; end if; end if; end process; end Behavioral;