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Found 304 results

  1. Hi, I'm using a nexys 3 sparten 6 fpga . I need to interface it with a keyboard, is there any core available to do that?
  2. Hello. I'm new to Verilog and I was assigned to code a servo controller in Verilog. The system clock runs at 50MHz. The period of the servo is 20ms, the minimum pulse width is 0.6ms (at 0 degrees), at 1.5ms for 90 degrees, and 2.4ms for 180 degrees. When the user presses one of the buttons on the FPGA and the button corresponds to increment, the servo has to move 5 degrees clockwise. If the user presses the button corresponding to decrement, the servo has to move 5 degrees counterclockwise. Please help me. I looked online for resources but I don't seem to understand them. Thank you so much in advance!
  3. sachin

    ethernet mac

    Hi, Can i have tutorial for bulding ethernet mac in nexys 3 board
  4. I want to store the image matrix into block RAM.In my UART receiver code I have instantiated BRAM module for writing purpose.Is this way is correct? Wheneve Instantiate there is not declring error.Where can I ear functionality of Block RAM
  5. Hello ! I'm currently encoutering an issue about how to assign each digit of a number on the seven segment display. For example, if I have the number 1932, how to affect the '2' on the first digit display . The '3' on the second, the '9' on the third, etc... Actually, I have a 4-bit BCD (which functions) and I want to display the decimal number. My output, bcd0, bcd1, bcd2, bcd3 represents the ones, the tens, the hundres and the thousands). I'm decoding each output like that : case bcd0 is when "0000"=> seven_seg<="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd1 is when "0000"=> seven_seg<="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd2 is when "0000"=> seven_seg <="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd3 is when "0000"=> seven_seg <="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; Of course, I know that I have to activate the 4 first anodes (low level). And that I have to assign each bit of "seven_seg" to the good pin on the .XCF file. Thank you very much for help !
  6. Dear Digilent Team, I have just reprogrammed the ft2232h eeprom in the FT_PROG. Now the Vivado says: "There is no current hw_target." So it looks that I were destroyed the EEPROM code in the nexys video. Could You send me a program to fix this issue ? Thank You. andrewna
  7. Hello! I'm currently working on a project and i need to use differential signaling. I'm using Arty development platform (designed around the Artix-7™ FPGA) and I have some problems in generating the two differential signals (P and N). I used an oscilloscope to check the signal that I want to be sent (MDO) by configuring it as a single ended signal and it is correct. But when I use OBUFDS the two differential signals are logic low all time. I put the verilog code below and the .xdc file configuration. Thank you very much! Have a good day! OBUFDS #( .IOSTANDARD("TMDS_33"), // Specify the output I/O standard .SLEW("FAST") // Specify the output slew rate ) OBUFDS_inst ( .O(ME_DIFF_P), // Diff_p output .OB(ME_DIFF_N), // Diff_n output .I(MDO) // Buffer input ); # .xdc file set_property PACKAGE_PIN U12 [get_ports ME_DIFF_P] set_property PACKAGE_PIN V12 [get_ports ME_DIFF_N] set_property IOSTANDARD TMDS_33 [get_ports ME_DIFF_P] set_property IOSTANDARD TMDS_33 [get_ports ME_DIFF_N] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_switching_activity -deassert_resets
  8. Hi! I've been playing with the low cost ESP8266 modules, that present a IP-over-WiFi as a serial device, and you use modem-like AT commands to control it. I've just put up a project that allows the FPGA to connect to my Wifi network, then send status message to a service that is listening on my Linux VM. It is all done using VHDL state machines (no software CPU), and could most probably be made a little more compact. Because the serial port is running at 9600 and the AT command based protocol overhead it is a pretty low bandwidth solution, but enough if you wanted to add some basic WiFi telemetry to a design. The ESP8266 module used was under $7 - http://www.seeedstudio.com/depot/WiFi-Serial-Transceiver-Module-w-ESP8266-p-1994.html You can find all the source on my Wiki at http://hamsterworks.co.nz/mediawiki/index.php/FPGA_ESP8266
  9. Hi, I am working on a unit that has Spartan 6 XC6SLX9 (TGFP144) devices. Each board has 1 Spartan 6 on it and each board is just a copy of the other (briefly, the unit is a 4 channel transmitter and I have each board handling 1 channel - so they are identical copies). I'm trying to find the best way to program these boards in the field remotely (so I can't rely on removing / attaching cables, pushing buttons etc.) One possible solution is to use this: http://store.digilentinc.com/jtag-smt2-nc-surface-mount-programming-module/ on my motherboard and daisy chain JTAG lines as per Xilinx docs. QUESTION: Can I use the JTAG-SMT2-NC with a full speed USB port (as opposed to a high speed USB port)? The USB hub we use on our motherboard is full speed only. I am not looking for any specific JTAG programming speeds. Second solution I have is to have an SPI flash for each FPGA and have them all on the same "shared" bus (the SPI flashes would be programmed by my uC on the motherboard). Since the FPGAs take control of the SPI bus on configuration, I'd be "de-coupling" the "shared" bus from the per-board bus with a buffer as shown below: http://imgur.com/a/jpsjx So when PROGRAM_B is raised to HIGH, the buffer tri-states its outputs (so the shared bus from other FPGAs is no longer in contention). QUESTION: Thoughts? Does this seem reasonable? I'm slightly leaning towards the first option - it seems more robust since JTAG was made to do the daisy chaining stuff -- but depends on whether full speed will work. Thanks, Aditya
  10. Hi, I'm new to FPGAs, so I purchased a BASYS3 to play around with. In following the "Getting Started with BASYS 3" video (youtube), I cannot save e a configuration to a memory device as that option is grayed out in my case (see attached screen capture). Does anyone have any ideas what's causing this and how to overcome it? Thanks in advance
  11. Hi, I tried to learn RS232 and created a project on Basys 3 with Pmod R232. The plan I would like to do is that whenever I set binary number at 8 switches on Basys 3, the data will be passed to the PC and I can see the character in the hyperterminal. At the same time, the LEDs for the "ON" switches with be turned on. I have successfully generated the bitstream file but it doesn't seems function. Include the Verilog code for transmitter, receiver and top modules. It will be great if someone can give hints to let me finish this project. P.S. I have used the logic from http://www.ece301.com/ Transmitter module transmitter( input clk, //clock input reset, // reset input transmit, //input to say transmission is ready, can be push button or switch input [7:0] data, // data transmitted output reg TxD // transmit data line ); reg TxDready; //register variable to tell when transmission is ready reg [3:0] bitcounter; //vector 4 bits counter to count up to 9 reg [13:0] counter; //vector 14 bits counter to count the baud rate, counter = clock / baud rate reg state, nextstate; // register state variable reg [9:0] rightshiftreg; // vector data needed to be transmitted 1 start, 8 data & 1 stop bit reg shift, load, clear; //register variable for shifting, loading the bits and clear the counter //counter logic always @ (posedge clk) //positive edge begin if (reset) begin // reset is asserted (reset = 1) state <=0; // state is idle (state = 0) counter <=0; // counter for baud rate is reset to 0 bitcounter <=0; //counter for bit transmission is reset to 0 end else begin counter <= counter + 1; //start counting if (counter >= 10415) //if count to 5207 because we start the conunt from 0, so not 5208 begin state <= nextstate; //state change to next state counter <=0; // reset counter to 0 if (load) rightshiftreg <= {1'b1,data,1'b0}; //load the data if load is asserted if (clear) bitcounter <=0; // reset the bitcounter if clear is asserted if (shift) begin // if shift is asserted rightshiftreg <= rightshiftreg >> 1; //right shift the data as we transmit the data from lsb bitcounter <= bitcounter + 1; //count the bitcounter end end end end //state machine always @ (state, bitcounter, transmit,rightshiftreg) //trigger by change of state, bitcounter or transmit begin load <=0; // set load equal to 0 at the beginning shift <=0; // set shift equal to 0 at the beginning clear <=0; // set clear equal to 0 at the beginning TxDready <=1; // set TxDReady equal to 1 so no transmission. When TxD is zero, the receiver knows it is transmitting TxD <=0; // set TxD equals to 0 at the beginning to avoid latch case (state) 0: begin // idle state if (transmit) begin // assert transmit input nextstate <=1; // set nextstate register variable to 1 to transmit state load <=1; // set load to 1 to prepare to load the data shift <=0; // set shift to 0 so no shift ready yet clear <=0; // set clear to 0 to avoid clear any counter end else begin // if transmit not asserted nextstate <=0; // next state is 0 back to idle TxDready <=1; // set TxD to 1 to avoid any transmission end end 1: begin // transmit state if (bitcounter >=9) begin // check if transmission is complete or not. If complete nextstate <= 0; // set nextstate back to 0 to idle state clear <=1; // set clear to 1 to clear all counters end else begin // if transmisssion is not complete nextstate <= 1; // set nextstate to 1 to stay in transmit state shift <=1; // set shift to 1 to continue shifting the data TxD <= rightshiftreg[0]; // shift the bit to output TxD end end default: begin // idle state if (transmit) begin // assert transmit input nextstate <=1; // set nextstate register variable to 1 to transmit state load <=1; // set load to 1 to prepare to load the data shift <=0; // set shift to 0 so no shift ready yet clear <=0; // set clear to 0 to avoid clear any counter end else begin // if transmit not asserted nextstate <=0; // next state is 0 back to idle TxDready <=1; // set TxD to 1 to avoid any transmission end end endcase end endmodule Receiver module receiver( input clk, //input clock input reset, //input reset input RxD, //input receving data line output [7:0]RxData // output for 8 bits data // output [7:0]LED // output 8 LEDs ); reg shift; // register variable shift to trigger shifting data reg state, nextstate; // register state variable reg [3:0] bitcounter; // register vector 4 bits counter to count up to 9 reg [3:0] samplecounter; // register vector 4 bits sample counter to count up to 9 reg [13:0] counter; // register vector 14 bits counter to count the baud rate reg [9:0] rxshiftreg; //register vector for bit shifting reg clear_bitcounter,inc_bitcounter,inc_samplecounter,clear_samplecounter; //register variable to clear or increment the counter assign RxData = rxshiftreg [8:1]; // assign the RxData // assign LED = RxData; // assign the LED output //counter logic always @ (posedge clk) begin if (reset)begin // if reset is asserted state <=0; // set state to idle bitcounter <=0; // reset the bit counter counter <=0; // reset the counter samplecounter <=0; // reset the sample counter end else begin // if reset is not asserted counter <= counter +1; // start count in the counter if (counter >= 3472) begin // if counter reach the baud rate with sampling counter <=0; //reset the counter state <= nextstate; // assign the state to nextstate if (shift)rxshiftreg <= {RxD,rxshiftreg[9:1]}; //if shift asserted, load the receiving data if (clear_samplecounter) samplecounter <=0; // if clear sampl counter asserted, reset sample counter if (inc_samplecounter) samplecounter <= samplecounter +1; //if increment counter asserted, start sample count if (clear_bitcounter) bitcounter <=0; // if clear bit counter asserted, reset bit counter if (inc_bitcounter)bitcounter <= bitcounter +1; // if increment bit counter asserted, start count bit counter end end end //state machine always @ (state or RxD or bitcounter or samplecounter or rxshiftreg) // triggered by change of state, Rxd and bit counter begin shift <= 0; // set shift to 0 to avoid any shifting clear_samplecounter <=0; // set clear sample counter to 0 to avoid reset inc_samplecounter <=0; // set increment sample counter to 0 to avoid any increment clear_bitcounter <=0; // set clear bit counter to 0 to avoid claring inc_bitcounter <=0; // set increment bit counter to avoid any count nextstate <=0; // set nextstate equals to 0 at the beginning to avoid any latch case (state) 0: begin // idle state if (RxD) // if input RxD data line asserted nextstate <=0; // back to idle state because RxD needs to be low to start transmission else begin // if input RxD data line is not asserted nextstate <=1; //jump to receiving state clear_bitcounter <=1; // trigger to clear bit counter clear_samplecounter <=1; // trigger to clear sample counter end end 1: begin // receiving state if (samplecounter==1) shift <=1; // if sample counter is 1, trigger shift if (samplecounter==3) begin // if sample counter is 3 as the sample rate used is 3 if (bitcounter ==9) begin // check if bit counter if 9 or not nextstate <= 0; // back to idle state if bit counter is 9 as receving is complete end inc_bitcounter <=1; // trigger the increment bit counter if bit counter is not 9 clear_samplecounter <=1; //trigger the sample counter to reset the sample counter end else inc_samplecounter <=1; // if sample is not equal to 3, keep counting end default: begin // idle state if (RxD) // if input RxD data line asserted nextstate <=0; // back to idle state because RxD needs to be low to start transmission else begin // if input RxD data line is not asserted nextstate <=1; //jump to receiving state clear_bitcounter <=1; // trigger to clear bit counter clear_samplecounter <=1; // trigger to clear sample counter end end endcase end endmodule Top module top( input btn0, input [8:0] sw, // input 8 switches , one for transmit input clk, input RxD, output TxD, output [7:0]LED // output 8 LEDs ); wire [7:0] data; assign data = sw; receiver R1 (.clk(clk), .reset(btn0), .RxD(RxD), .RxData(LED)); transmitter T1 (.clk(clk),.transmit(sw[8]), .reset(btn0),.data(sw[7:0]), .TxD(TxD)); endmodule
  12. Hi, I am using Xilinx Zynq UltraScale+ MPSoC ZCU102 Evaluation Kit and I am newbie for using this board. I'm following this link to generate an interrupt using GPIO switches and turn off a led : http://www.wiki.xilinx.com/Linux+GPIO+Driver. The drivers works correctly and the led is heartbeating, when i check /proc/interrupts i get: ... 223: 0 0 0 0 GICv2 154 Level fd4c0000.dma 224: 0 0 0 0 xgpio 0 Edge sw14 233: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1 ... but when i switch on cpu stops and i get this error: root@Xilinx-ZCU102-2016_1:~# [ 18.111391] Unable to handle kernel paging request at virtual address b9410a80aa13043f [ 18.119243] pgd = ffffffc87ad07000 [ 18.122615] [b9410a80aa13043f] *pgd=0000000000000000, *pud=0000000000000000 [ 18.129559] Internal error: Oops: 96000004 [#1] SMP [ 18.134420] Modules linked in: [ 18.137460] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.4.0 #78 [ 18.143361] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.148136] task: ffffffc00224efc0 ti: ffffffc002240000 task.ti: ffffffc002240000 [ 18.155613] PC is at xgpio_irqhandler+0x2c/0x144 [ 18.160202] LR is at xgpio_irqhandler+0x1c/0x144 [ 18.164801] pc : [<ffffffc0003c8ee0>] lr : [<ffffffc0003c8ed0>] pstate: 600001c5 [ 18.172185] sp : ffffffc002243d00 [ 18.175476] x29: ffffffc002243d00 x28: 0000000000000000 [ 18.180769] x27: 0000000000000000 x26: ffffffc0022c2000 [ 18.186063] x25: ffffffc00078acf0 x24: ffffff8000015000 [ 18.191358] x23: ffffffc0003c8eb4 x22: b9410a80aa1303f7 [ 18.196653] x21: 0000000000000000 x20: 0000000000000000 [ 18.201948] x19: ffffffc002227000 x18: 0000000000000001 [ 18.207242] x17: 0000000000000006 x16: ffffffbe1dae9f68 [ 18.212537] x15: ffffffc87b08f000 x14: 0000000000000007 [ 18.217832] x13: ffffffc87b801128 x12: 0000004000000000 [ 18.223127] x11: ffffffc002246000 x10: 00000000000006e0 [ 18.228422] x9 : ffffffc002243e70 x8 : ffffffc87b400058 [ 18.233716] x7 : ffffffc87b400d88 x6 : 0000000000000002 [ 18.239011] x5 : 00000000fffffffa x4 : ffffffc87b400d89 [ 18.244306] x3 : 0000000000000000 x2 : 0000000000000000 [ 18.249601] x1 : 0000000000000020 x0 : 0000000000000000 [ 18.254895] [ 18.256373] Process swapper/0 (pid: 0, stack limit = 0xffffffc002240020) [ 18.263060] Stack: (0xffffffc002243d00 to 0xffffffc002244000) [ 18.268790] 3d00: ffffffc002243d50 ffffffc0000d1088 ffffffc002227000 0000000000000000 [ 18.276609] 3d20: 0000000000000000 ffffffc002249040 ffffff8000014010 ffffffc0000d13cc [ 18.284421] 3d40: ffffffc002243d50 ffffffc0000d107c ffffffc002243d60 ffffffc0000d13a0 [ 18.292232] 3d60: ffffffc002243da0 ffffffc000080cec ffffff800001400c ffffffc002279000 [ 18.300045] 3d80: ffffffc002243de0 ffffffc0000e5ed0 ffffffc87b808000 00000079000ec410 [ 18.307857] 3da0: ffffffc002243f00 ffffffc000083da8 ffffffc002240000 ffffffc002246000 [ 18.315668] 3dc0: ffffffc002243f00 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.323480] 3de0: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.331292] 3e00: 0000000000000000 000000001999999a 002aad4b00000000 00000000fffeecaa [ 18.339104] 3e20: 00000000fffeecab ffffffc002243e70 00000000000006e0 ffffffc002246000 [ 18.346916] 3e40: 0000004000000000 ffffffc87b801128 0000000000000007 ffffffc87b08f000 [ 18.354729] 3e60: ffffffbe1dae9f68 0000000000000006 0000000000000001 ffffffc002240000 [ 18.362541] 3e80: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc002243f20 [ 18.370352] 3ea0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.378164] 3ec0: 0000000000000000 ffffffc002243f00 ffffffc000084e6c ffffffc002243f00 [ 18.385977] 3ee0: ffffffc000084e70 0000000060000145 ffffffc00078acf0 ffffffc00077c278 [ 18.393789] 3f00: ffffffc002243f10 ffffffc0000ca2e0 ffffffc002243f20 ffffffc0000ca418 [ 18.401600] 3f20: ffffffc002243f90 ffffffc000779080 ffffffc0022c5000 ffffffc0022c5000 [ 18.409413] 3f40: ffffffc0022c5000 ffffffc002246000 ffffffc87ffa2580 ffffffc000a6fca8 [ 18.417224] 3f60: 000000000231c000 000000000231f000 ffffffc0000801d8 0000000000000000 [ 18.425037] 3f80: ffffffc002243f90 ffffffc000779078 ffffffc002243fa0 ffffffc000a3d94c [ 18.432848] 3fa0: 0000000000000000 0000000000780000 0000000000000000 0000000000000e12 [ 18.440660] 3fc0: 0000000004080000 0000000000000000 0000000000000000 0000000000000000 [ 18.448472] 3fe0: 0000000000000000 ffffffc000a6fca8 0000000000000000 0000000000000000 [ 18.456281] Call trace: [ 18.458707] [<ffffffc0003c8ee0>] xgpio_irqhandler+0x2c/0x144 [ 18.464353] [<ffffffc0000d1088>] generic_handle_irq+0x24/0x38 [ 18.470079] [<ffffffc0000d13a0>] __handle_domain_irq+0x60/0xac [ 18.475895] [<ffffffc000080cec>] gic_handle_irq+0x60/0xb4 [ 18.481274] Exception stack(0xffffffc002243db0 to 0xffffffc002243ed0) [ 18.487699] 3da0: ffffffc002240000 ffffffc002246000 [ 18.495518] 3dc0: ffffffc002243f00 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.503329] 3de0: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.511142] 3e00: 0000000000000000 000000001999999a 002aad4b00000000 00000000fffeecaa [ 18.518954] 3e20: 00000000fffeecab ffffffc002243e70 00000000000006e0 ffffffc002246000 [ 18.526766] 3e40: 0000004000000000 ffffffc87b801128 0000000000000007 ffffffc87b08f000 [ 18.534578] 3e60: ffffffbe1dae9f68 0000000000000006 0000000000000001 ffffffc002240000 [ 18.542390] 3e80: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc002243f20 [ 18.550202] 3ea0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.558013] 3ec0: 0000000000000000 ffffffc002243f00 [ 18.562868] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 18.567643] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 18.573284] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 18.579101] [<ffffffc000779080>] rest_init+0x74/0x7c [ 18.584049] [<ffffffc000a3d94c>] start_kernel+0x394/0x3a8 [ 18.589427] [<0000000000780000>] 0x780000 [ 18.593421] Code: b4000820 f9400800 f9400414 f9401ef6 (f94026c0) [ 18.599503] ---[ end trace fc72e20977be1640 ]--- [ 18.604096] Kernel panic - not syncing: Fatal exception in interrupt [ 18.610435] CPU3: stopping [ 18.613125] CPU: 3 PID: 0 Comm: swapper/3 Tainted: G D 4.4.0 #78 [ 18.620241] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.625013] Call trace: [ 18.627447] [<ffffffc000087da8>] dump_backtrace+0x0/0x114 [ 18.632829] [<ffffffc000087ed0>] show_stack+0x14/0x1c [ 18.637865] [<ffffffc000393cf8>] dump_stack+0x84/0xa0 [ 18.642897] [<ffffffc00008d4cc>] handle_IPI+0x18c/0x1a0 [ 18.648104] [<ffffffc000080d28>] gic_handle_irq+0x9c/0xb4 [ 18.653486] Exception stack(0xffffffc87b8efdf0 to 0xffffffc87b8eff10) [ 18.659910] fde0: ffffffc87b8ec000 ffffffc002246000 [ 18.667730] fe00: ffffffc87b8eff40 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.675541] fe20: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.683353] fe40: 0000000000000000 000000001999999a 000a037a00000000 00000000fffeed1b [ 18.691165] fe60: 00000000fffeed1c ffffffc87b8efeb0 00000000000006e0 0000000000000005 [ 18.698977] fe80: ffffffc00078b5d4 ffffffc073ad7b80 ffffffc87b325380 ffffffc87ba30000 [ 18.706789] fea0: ffffffbe1db0baa0 0000000000000006 0000000000000001 ffffffc87b8ec000 [ 18.714601] fec0: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc87b8eff60 [ 18.722413] fee0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.730224] ff00: 0000000000000000 ffffffc87b8eff40 [ 18.735078] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 18.739853] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 18.745496] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 18.751310] [<ffffffc00008cfcc>] secondary_start_kernel+0x11c/0x140 [ 18.757559] [<000000000008103c>] 0x8103c [ 18.761464] CPU2: stopping [ 18.764157] CPU: 2 PID: 0 Comm: swapper/2 Tainted: G D 4.4.0 #78 [ 18.771273] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.776045] Call trace: [ 18.778479] [<ffffffc000087da8>] dump_backtrace+0x0/0x114 [ 18.783861] [<ffffffc000087ed0>] show_stack+0x14/0x1c [ 18.788895] [<ffffffc000393cf8>] dump_stack+0x84/0xa0 [ 18.793929] [<ffffffc00008d4cc>] handle_IPI+0x18c/0x1a0 [ 18.799136] [<ffffffc000080d28>] gic_handle_irq+0x9c/0xb4 [ 18.804518] Exception stack(0xffffffc87b8ebdf0 to 0xffffffc87b8ebf10) [ 18.810942] bde0: ffffffc87b8e8000 ffffffc002246000 [ 18.818762] be00: ffffffc87b8ebf40 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.826573] be20: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.834385] be40: 0000000000000000 000000001999999a 000f424000000000 00000000fffeed31 [ 18.842197] be60: 00000000fffeed32 ffffffc87b8ebeb0 00000000000006e0 ffffffc002246000 [ 18.850009] be80: 0000004000000000 ffffffc87b801128 000000000000001c ffffffc87ac9c000 [ 18.857821] bea0: ffffffbe1dadc240 0000000000000006 0000000000000001 ffffffc87b8e8000 [ 18.865633] bec0: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc87b8ebf60 [ 18.873445] bee0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 18.881256] bf00: 0000000000000000 ffffffc87b8ebf40 [ 18.886110] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 18.890885] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 18.896527] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 18.902342] [<ffffffc00008cfcc>] secondary_start_kernel+0x11c/0x140 [ 18.908591] [<000000000008103c>] 0x8103c [ 18.912496] CPU1: stopping [ 18.915188] CPU: 1 PID: 0 Comm: swapper/1 Tainted: G D 4.4.0 #78 [ 18.922305] Hardware name: ZynqMP ZCU102 RevB (DT) [ 18.927077] Call trace: [ 18.929511] [<ffffffc000087da8>] dump_backtrace+0x0/0x114 [ 18.934893] [<ffffffc000087ed0>] show_stack+0x14/0x1c [ 18.939927] [<ffffffc000393cf8>] dump_stack+0x84/0xa0 [ 18.944961] [<ffffffc00008d4cc>] handle_IPI+0x18c/0x1a0 [ 18.950168] [<ffffffc000080d28>] gic_handle_irq+0x9c/0xb4 [ 18.955550] Exception stack(0xffffffc87b8e3df0 to 0xffffffc87b8e3f10) [ 18.961974] 3de0: ffffffc87b8e0000 ffffffc002246000 [ 18.969794] 3e00: ffffffc87b8e3f40 ffffffc000084e70 0000000060000145 ffffffc002228f40 [ 18.977605] 3e20: 0000000000000000 0000000000000000 0000000000000001 0000000000000000 [ 18.985417] 3e40: 0000000000000000 000000001999999a 000cdfe600000000 00000000fffeed27 [ 18.993229] 3e60: 00000000fffeed28 ffffffc87b8e3eb0 00000000000006e0 ffffffc002246000 [ 19.001041] 3e80: 0000004000000000 ffffffc87b801128 000000000000000e ffffffc87b3de000 [ 19.008853] 3ea0: ffffffbe1daf58b0 0000000000000006 0000000000000001 ffffffc87b8e0000 [ 19.016665] 3ec0: ffffffc002246000 ffffffc002246ad0 ffffffc0022259c0 ffffffc87b8e3f60 [ 19.024477] 3ee0: ffffffc002228f40 ffffffc00078acf0 ffffffc0022c2000 0000000000000000 [ 19.032288] 3f00: 0000000000000000 ffffffc87b8e3f40 [ 19.037142] [<ffffffc000083da8>] el1_irq+0x68/0xc0 [ 19.041917] [<ffffffc0000ca2e0>] default_idle_call+0x1c/0x30 [ 19.047559] [<ffffffc0000ca418>] cpu_startup_entry+0x124/0x1dc [ 19.053374] [<ffffffc00008cfcc>] secondary_start_kernel+0x11c/0x140 [ 19.059623] [<000000000008103c>] 0x8103c [ 19.063529] ---[ end Kernel panic - not syncing: Fatal exception in interrupt This is my pl.dtsi: / { amba_pl: amba_pl { #address-cells = <2>; #size-cells = <2>; compatible = "simple-bus"; ranges ; axi_gpio_0: gpio@80000000 { #gpio-cells = <2>; #interrupt-cells = <2>; compatible = "xlnx,xps-gpio-1.00.a"; gpio-controller ; interrupt-controller ; interrupt-parent = <&gic>; interrupts = <0 89 1>; reg = <0x0 0x80000000 0x0 0x10000>; xlnx,all-inputs = <0x1>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x0>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x00000000>; xlnx,dout-default-2 = <0x00000000>; xlnx,gpio-width = <0x8>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x1>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xFFFFFFFF>; xlnx,tri-default-2 = <0xFFFFFFFF>; }; gpio-keys { compatible = "gpio-keys"; #address-cells = <1>; #size-cells = <0>; autorepeat; sw14 { label = "sw14"; gpios = <&axi_gpio_0 0 0>; linux,code = <108>; /* down */ gpio-key,wakeup; autorepeat; }; }; axi_gpio_1: gpio@80010000 { #gpio-cells = <2>; compatible = "xlnx,xps-gpio-1.00.a"; gpio-controller ; reg = <0x0 0x80010000 0x0 0x10000>; xlnx,all-inputs = <0x0>; xlnx,all-inputs-2 = <0x0>; xlnx,all-outputs = <0x1>; xlnx,all-outputs-2 = <0x0>; xlnx,dout-default = <0x00000000>; xlnx,dout-default-2 = <0x00000000>; xlnx,gpio-width = <0x8>; xlnx,gpio2-width = <0x20>; xlnx,interrupt-present = <0x0>; xlnx,is-dual = <0x0>; xlnx,tri-default = <0xFFFFFFFF>; xlnx,tri-default-2 = <0xFFFFFFFF>; }; gpio-leds { compatible = "gpio-leds"; led-ds23 { label = "led-ds23"; gpios = <&axi_gpio_1 0 0>; default-state = "on"; linux,default-trigger = "heartbeat"; }; }; }; };
  13. Good Day, I looked on the forum to see if this question was answered. While I saw hints to the answer, it wasn't clear. If this is a repeat, my apologies. I just purchased one of the Anvyl boards during the end of year sale. While I have ISE and Vivado both installed, I generally use Vivado only now for my Nexys4 DDR and ZedBoard, If possible, I'd like to use Vivado for designs on the Anvyl. Is this possible? If so, are their any Vivado board files available for this board (I searched but couldn't find any), or is it just a matter of me configuring the right FPGA and converting the info in the UCF file to a set of Vivado constraints? Thanks, Dave
  14. Hello! My task is creation of real-time system which can draw simple graphics figure on monitor (VGA) when the system register input pulse. The main difficulty is to draw this image only once (for measuring man's reaction time: time between image drawing and the button pressing). I think it'll possible to use FPGA to register input pulse and to generate VGA signal with required parameters. But I don't undestand can the ONLY ONE image frame be drawn at input pulse interrupting or not? The main task is to minimize time delays and in this case I can't use the standart solutions. For example, using Raspberry Pi or a similar device is accompanied by the necessary of screen refreshing and image drawing binding. This adds a random time delay from 0ms (if the screen refresh time coincides with time of input external pulse which starts drawing figures) to 1/60Hz=16.7ms. I need your advices or suggestions. Thanks!
  15. Hi. I want to generate 15MHz clock from 40MHz system clock. I could use DCM to generate this clock but i want to use counter for that purpose. Can someone tell me that how can i do that?
  16. bakytzhan

    Divide a clock signal

    Hello everybody! Guys, I wanted to ask How to do a seconds, minutes signal with Basys 3 ? How can I delay a 100 Mhz clock?
  17. Hi. I'm new to programming FPGAs. I just would like to ask, what are the recommended FPGA boards for beginners? My university currently uses the Spartan 3E Starter Board but from the reviews that I've read, the Spartan 3E is quite old already and some say that I should consider buying other FPGA boards that have more functionalities and processing power.
  18. I have an Arty board and USBUART Pmod card. I want to send data from Windows to FPGA on Arty via USBUART Pmod. First, can this be done, and how? Is there ref. design? Thanks.
  19. aysekban

    Basys3, TW-131

    Hi, I have an TW-131 coin acceptor. That has three cables, one is connected to 12V, one is ground and one is for the pulse. When money is inserted the white cable gives a pulse for 50ms. I am not sure how to connect this coin acceptor to BASYS3 board. I mean to which part of the BASYS3 do I need to connect the white cable. Also I am not sure about how to write a code that gives an output "1" when money inserted to con acceptor and "0" when no money is inserted. Can you help me?
  20. Hi. I want to interface EEPROM with the FPGA. Can someone tell me that what is the general size of EEPROM to be attach with Virtex 4 FPGA? Thanks
  21. HI guys ; please i want a some help; i want to connect Nexys 4 board with RTLSDR receiver and get data from him and do processing in FPGA , some people tell me it is hard with VHDL and they propose to do this with microblaze , i need some help to do this , (advices , tutorial ....). thanks
  22. Hello, I have ordered the Artix-7 35T "Arty" FPGA Evaluation Kit to educate FPGA design (VHDL) using Vivado tool. Today, I am looking for some starting points: tutorials, websites, books, online courses, ... All help & tips are welcome. Thanks. JrV
  23. Hi, i need to change the eeprom a little to achieve my communication tasks I need the whole file(firmware source program) in order to understand it and achieve my needs by using it. who can help me! Thank you very much!
  24. Hi, i need to change the eeprom a little to achieve my communication tasks I need the whole file(firmware source program) in order to understand it and achieve my needs by using it. Thank you very much!