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Found 313 results

  1. Hi, I am trying to rebuild the arty z7 petalinux BSP as per the instructions given by them here https://github.com/Digilent/petalinux-bsps/wiki/Quick-Start-Guide-for-Arty-Z7. But when I try the command $ petalinux-boot --jtag --prebuilt 3, I get an error saying [skaat27@localhost Digilent-Arty-Z7-Linux-BD-v2016.2]$ petalinux-boot --jtag --prebuilt 3 ERROR: No subsystem configuration file can be find in the project. sh: lsb_release: command not found webtalk failed:Invalid tool in the statistics file:petalinux-yocto! webtalk failed:Failed to get PetaLinux usage statistics! Anybody knows what the issue is? Karthik
  2. skaat27

    Arty Z7 HDMI IN issue

    Hello Guys, I just received my Arty Z7 board and I was trying out the HDMI_IN design. I exactly followed the given instructions and I get this place_design error in vivado and "The Hardware Project referenced by this BSP (hdmi_in_bsp) was not found in this workspace." in sdk. I tried out the HDMI_OUT and it was working perfectly fine. I have attached the screenshots. Kindly help me out here. Note: I have seen similar questions on this forum, but none of those solutions helped me. So starting a new thread. TIA Regards, Karthik
  3. hello, I want to interface zedboard(PL-Section) with external ad7768-4 ADC board using SPI interface via FMC_LPC connector. i have following questions: 1) how i can set SPI interface in zedboard (i mean, where i can assign "sclk, cs#, sdi, sdo" pins from ad7768-4 adc board to zedboard(PL-section) ) ? 2) can I access QSPI Flash by using PL-section of zynq 7000 ? 3) what is the meaning of QSPI Feedback, where it should be connected? 4) can i use QSPI in standard mode ? please help me ! Thank you
  4. Good afternoon someone knows how to implement a UART communication protocol in l nexys 4 for the XADC, someone who can explain it to me and how to implement it?
  5. I have a Z-Turn FPGA, based around a Xilinx Zynq 7020. Unfortunately, its JTAG port is 2x7 with 2.54mm pitch. I just realized the HS3 uses 2.00mm pitch. Is there a recommended way to convert the pin pitch? I designed my own board, but an existing option would be more convenient.
  6. I am currently using nexys 4, I want to input console inputs to my VHDL design. I know that ISE uses a .ucf file where the inputs and outputs of the card are assigned, however my interest is not to use the inputs provided by the card and I do not know how to assign these inputs sent from an application, I would thank anyone who can help.
  7. Hello, We are a company based in Pittsburgh, Pennsylvania, and we are looking for a contractor who has experience with FPGA design work. Thank you.
  8. i want to generate sine wave on dac (pmodda3)(http://www.analog.com/media/en/technical-documentation/data-sheets/AD5541A.pdf)and i am using spartan3e but there ara several warnings ,How can i fix the warnings? i loaded code and picture. help me please ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_arith.all; use ieee.std_logic_signed.all; use ieee.numeric_std.all; entity kecelikalem is port( clk: in STD_LOGIC; reset : in STD_LOGIC; din:out std_logic; ldac:out std_logic:='1'; cs :out std_logic:='1'; sclk :out std_logic:='1'); end kecelikalem; architecture Behavioral of kecelikalem is signal a:integer range 0 to 3:=0; signal i : integer range 0 to 18:=0; type veri is array (2 downto 0) of std_logic_vector(15 downto 0); signal sine :veri:=("1100000000100000","0000000000001111","1100000000000000"); --signal sine :std_logic_vector(15 downto 0):="1100000000000011"; signal data :std_logic_vector(15 downto 0); signal temporal: STD_LOGIC; signal counter : integer range 0 to 124999 := 0; begin frequency_divider: process (reset, clk) begin if (reset = '1') then temporal <= '0'; counter <= 0; elsif rising_edge(clk) then if (counter = 124999) then temporal <= NOT(temporal); counter <= 0; else counter <= counter + 1; end if; end if; end process; sclk <= temporal; process (temporal) begin if falling_edge(temporal) then if(a=3) then a<=0; else data<=sine(a); if (i=18) then a<=a+1; ldac<='1'; i<=0; else if (i=17) then ldac <='0'; else if (i=16) then cs<='1'; ldac <='1'; else cs<='0'; din<=data(i); --din<=sine(i); ldac <='1'; end if ; end if; end if ; i<=i+1; end if; end if; end process; end Behavioral;
  9. Hi! I've hooked up a CMOD-A7 to an audio codec board designed for the Raspberry Pi, getting ready to play with some audio. You can find the VHDL source at http://hamsterworks.co.nz/mediawiki/index.php/STGL5000#sgtl5000_interface.vhd It is still rough and ready, but it works
  10. hello, i'm new born baby in embedded system. I want to establish a communication between ADC Board to Zedboard(PL-section-xc7z020) via LPC-FMC connector. please tell me lpc fmc pin out and how those pins connected to PL(FPGA) Section of zynq (like any diagram). please help me, Thank you.
  11. Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  12. 1.What is the exact difference between the board and the platform? 2.Are there usable platforms without SoC or any processor on them? 3. How can be the boards connected to each other?
  13. Where can I see the relations between the Arty Z7 board pins (I/O) and the FPGA pins? In "Arty Z7 Reference Manual" it is not enough information: only buttons, slide switches, LEDs and HDMI pins relations appear. (eg. BTN0 is D19) What about the rest of the pins (I/O)?
  14. Hai ., i had bought DIGILENT Zybo Kit 7000 series Family. i had flashed the Zynq boot image with the following offset values successfully on Zynq Board via Xilinx SDK (ver: 2016.4) fsbl.elf system_wrapper.bit U-boot.elf U-image 0x600000 dtb file 0xA00000 ramdisk 0xA20000 But the FPGA done_led is not working automatically after a power cycle. on the other hand, if i program the FPGA MANUALLY via Xilinx SDK , it works and kernel image loads successfully from QSPI Flash. How to Make FPGA done_LED works automatically? Thanks in Advance..
  15. Hi All, I have been working through the Arty - Getting Started with Microblaze project in the resource folder with the Artix-7 FPGA Development Board. When I get to step 11.2 Program the FPGA I get the following message Program FPGA failed Reason: Could not find FPGA device on the board for connection 'Local'. I have been stuck here for the last couple week and have tried several times to track down the connection issue. So far no luck. Any assistance would be greatly appreciated. Thanks, Don
  16. Hello everybody! I just finished a series of posts on zipcpu.com describing how a debugging access can be created out of the serial port to provide access into the internals of an FPGA. Examples include how you can read or write FPGA block RAM, or even an internal scope. Today's post described how to build a software facility for accessing memory mapped I/O components within your design. Hence, you can issue read and write commands from your host PC software to access the internals of your design. In many ways, this design was motivated by requests on the forum asking for help while trying to debug an FFT (as one example). It's a similar, albeit simpler, debugging component to the one I've used myself for debugging designs. Indeed, I've used the concept presented to debug flash controllers, block RAM, wishbone bus components, the ZipCPU, the ICAPE configuration interface, and much more. In addition to the articles on zipcpu.com, you can also find all of the code posted on GitHub and licensed under LGPL--should you wish to try it out yourself, or even modify it for your own design. Even better, since the design is built of entirely open source components, you can build a Verilator simulation and simulate your entire design, a capability many students have struggled to do with their designs. Not only that, you can also integrate your own components into the design, while continuing to simulate all of the logic within the design. Dan
  17. mihai5

    Timer on bare metal app

    Hi, I want to measure elapsed time in a bare-metal application on the Xilinx Zynq SoC(zedboard). I included "xtime_l.h" and used XTime_GetTime(&tStart) and XTime_GetTime(&tEnd) to populate tStart and tEnd. The difference tEnd – tStart always gives me 0 for whatever instructions I put between XTime_GetTime(&tStart) and XTime_GetTime(&tEnd). Instructions between XTime_GetTime(&tStart) and XTime_GetTime(&tEnd) that I put are: ————————————- XTime_GetTime(&tStart); print(“Hello World\n\r”); for(int i=0;i< 1000 ;i++) { sum += i; } Xil_Out32(0x43c00000, 0x5); Xil_Out32(0x7aa00000, 0x5555); NumberOfPattern = Xil_In32(0x43c00004); XTime_GetTime(&tEnd) ————————————- I need to mention that i did not configure the PL part to include an axi_timer IP. I did not do this because, as i read, this uses the global timer in the zynq Soc whose counter increases every two clock cycles. Can someone to show me where is the mistake and give me some advices?
  18. Hi, I want to implement in Vivado a hardware implementation which will program the FPGA to create 4 register of 128 bit data and 4 comparators. First entries of the comparators will be linked to these 4 registers and the other entries will be linked to a single 128 bit register received from PS. I attached i picture (A picture is worth a thousand words). Please guide me with an exemple, start point in solving this issue.
  19. mihai5

    Init PS

    Hi, I'm using XSDB shell to initialize my soc on zedboard. When I hit the command "xsdb% ps7_init" i get the error "AP transaction error, DAP status f0000021". Is there someone who met this error and can provide me a hint?
  20. Hi, I just bought a Zybo FPGA Dev board from Digikey and tried to power it up using USB. But I cannot see any indication of whether the board is alive, i.e. LED (LD11) is not ON. The J7 is set for powering up via USB. I am quite new to this and would really appreciate some help. Thanks!
  21. I'm using the Nexys Video board, and I followed https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-programming-guide/start this tutorial and use JTAG to program it. However, data and program are lost when power is off and I have to re-configure the board. What should I do to have the program launched automatically every time the power is on? Through the tutorial mentioned above, I understand that I need a Quad SPI Flash, should I just follow the section N°5? By the way, once the program is stored, how to modify? If I use a QSPI flash, do I just need to create a new bitstream and repeat the instructions in section n°5?
  22. Hi @jpeyron, yes my questions are: how to build the sdk for petalinux on windows 7? how to build the BOOT.bin for example of Sobel filter on windows 7? how to build the u-boot for example of Sobel filter on windows 7? thanks.
  23. Hello everyone, I kindly ask for some start points that may help me in developing an linux application, on zedboard that inspect the payload of tcp/udp package received through eth interface. I had search a lot on internet/forums about this subject but i could not find some strong hints.
  24. I've finally broken the back of DisplayPort, and have a 800x600 colour bar picture showing using my Nexys Video. Still a lot of work to go before I get UHD resolutions working and a nice generic interface, but all the low-level base technology stuff is working. I started on August 12th, so it has taken over a solid month of hobby time to get this far! Source is on Github at https://github.com/hamsternz/FPGA_DisplayPort and some notes are on my Wiki at http://hamsterworks.co.nz/mediawiki/index.php/DisplayPort Currently sits at about 9,000 lines of VHDL... but only needs 610 LUTs and 680 flipflops.
  25. This little module might be of use to somebody - it sends 16-bit values to an external serial device, as four ascii hexidecimal digits (eg "12AB"), with new lines and carriage returns. http://hamsterworks.info/index.php/Hw_tx_binary_as_ascii The sample design send the settings of the 16 slide switches every time the center button is pressed.