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Found 304 results

  1. hello, i'm new born baby in embedded system. I want to establish a communication between ADC Board to Zedboard(PL-section-xc7z020) via LPC-FMC connector. please tell me lpc fmc pin out and how those pins connected to PL(FPGA) Section of zynq (like any diagram). please help me, Thank you.
  2. Hi - I just tried to install the XUP USB-JTAG Programming Cable from diligent. I also have a Diligent Programming Cable. Centos can see both cables (see below) Vivado can see the Diligent programming cable but not the Xilinx one. Given the physical constraints of the installation only the Xilinx one will work. Are there any specific instructions to get the Xilinx cable going? $lsusb | grep "Xilinx/|Future" Bus 002 Device 003: ID 03fd:000d Xilinx, Inc. Bus 001 Device 006: ID 0403:6014 Future Technology Devices International, Ltd FT232H Single HS USB-UART/FIFO IC
  3. 1.What is the exact difference between the board and the platform? 2.Are there usable platforms without SoC or any processor on them? 3. How can be the boards connected to each other?
  4. Where can I see the relations between the Arty Z7 board pins (I/O) and the FPGA pins? In "Arty Z7 Reference Manual" it is not enough information: only buttons, slide switches, LEDs and HDMI pins relations appear. (eg. BTN0 is D19) What about the rest of the pins (I/O)?
  5. Hai ., i had bought DIGILENT Zybo Kit 7000 series Family. i had flashed the Zynq boot image with the following offset values successfully on Zynq Board via Xilinx SDK (ver: 2016.4) fsbl.elf system_wrapper.bit U-boot.elf U-image 0x600000 dtb file 0xA00000 ramdisk 0xA20000 But the FPGA done_led is not working automatically after a power cycle. on the other hand, if i program the FPGA MANUALLY via Xilinx SDK , it works and kernel image loads successfully from QSPI Flash. How to Make FPGA done_LED works automatically? Thanks in Advance..
  6. Hi All, I have been working through the Arty - Getting Started with Microblaze project in the resource folder with the Artix-7 FPGA Development Board. When I get to step 11.2 Program the FPGA I get the following message Program FPGA failed Reason: Could not find FPGA device on the board for connection 'Local'. I have been stuck here for the last couple week and have tried several times to track down the connection issue. So far no luck. Any assistance would be greatly appreciated. Thanks, Don
  7. Hello everybody! I just finished a series of posts on describing how a debugging access can be created out of the serial port to provide access into the internals of an FPGA. Examples include how you can read or write FPGA block RAM, or even an internal scope. Today's post described how to build a software facility for accessing memory mapped I/O components within your design. Hence, you can issue read and write commands from your host PC software to access the internals of your design. In many ways, this design was motivated by requests on the forum asking for help while trying to debug an FFT (as one example). It's a similar, albeit simpler, debugging component to the one I've used myself for debugging designs. Indeed, I've used the concept presented to debug flash controllers, block RAM, wishbone bus components, the ZipCPU, the ICAPE configuration interface, and much more. In addition to the articles on, you can also find all of the code posted on GitHub and licensed under LGPL--should you wish to try it out yourself, or even modify it for your own design. Even better, since the design is built of entirely open source components, you can build a Verilator simulation and simulate your entire design, a capability many students have struggled to do with their designs. Not only that, you can also integrate your own components into the design, while continuing to simulate all of the logic within the design. Dan
  8. mihai5

    Timer on bare metal app

    Hi, I want to measure elapsed time in a bare-metal application on the Xilinx Zynq SoC(zedboard). I included "xtime_l.h" and used XTime_GetTime(&tStart) and XTime_GetTime(&tEnd) to populate tStart and tEnd. The difference tEnd – tStart always gives me 0 for whatever instructions I put between XTime_GetTime(&tStart) and XTime_GetTime(&tEnd). Instructions between XTime_GetTime(&tStart) and XTime_GetTime(&tEnd) that I put are: ————————————- XTime_GetTime(&tStart); print(“Hello World\n\r”); for(int i=0;i< 1000 ;i++) { sum += i; } Xil_Out32(0x43c00000, 0x5); Xil_Out32(0x7aa00000, 0x5555); NumberOfPattern = Xil_In32(0x43c00004); XTime_GetTime(&tEnd) ————————————- I need to mention that i did not configure the PL part to include an axi_timer IP. I did not do this because, as i read, this uses the global timer in the zynq Soc whose counter increases every two clock cycles. Can someone to show me where is the mistake and give me some advices?
  9. Hi, I want to implement in Vivado a hardware implementation which will program the FPGA to create 4 register of 128 bit data and 4 comparators. First entries of the comparators will be linked to these 4 registers and the other entries will be linked to a single 128 bit register received from PS. I attached i picture (A picture is worth a thousand words). Please guide me with an exemple, start point in solving this issue.
  10. mihai5

    Init PS

    Hi, I'm using XSDB shell to initialize my soc on zedboard. When I hit the command "xsdb% ps7_init" i get the error "AP transaction error, DAP status f0000021". Is there someone who met this error and can provide me a hint?
  11. Hi, I just bought a Zybo FPGA Dev board from Digikey and tried to power it up using USB. But I cannot see any indication of whether the board is alive, i.e. LED (LD11) is not ON. The J7 is set for powering up via USB. I am quite new to this and would really appreciate some help. Thanks!
  12. I'm using the Nexys Video board, and I followed this tutorial and use JTAG to program it. However, data and program are lost when power is off and I have to re-configure the board. What should I do to have the program launched automatically every time the power is on? Through the tutorial mentioned above, I understand that I need a Quad SPI Flash, should I just follow the section N°5? By the way, once the program is stored, how to modify? If I use a QSPI flash, do I just need to create a new bitstream and repeat the instructions in section n°5?
  13. Hi @jpeyron, yes my questions are: how to build the sdk for petalinux on windows 7? how to build the BOOT.bin for example of Sobel filter on windows 7? how to build the u-boot for example of Sobel filter on windows 7? thanks.
  14. Hello everyone, I kindly ask for some start points that may help me in developing an linux application, on zedboard that inspect the payload of tcp/udp package received through eth interface. I had search a lot on internet/forums about this subject but i could not find some strong hints.
  15. I've finally broken the back of DisplayPort, and have a 800x600 colour bar picture showing using my Nexys Video. Still a lot of work to go before I get UHD resolutions working and a nice generic interface, but all the low-level base technology stuff is working. I started on August 12th, so it has taken over a solid month of hobby time to get this far! Source is on Github at and some notes are on my Wiki at Currently sits at about 9,000 lines of VHDL... but only needs 610 LUTs and 680 flipflops.
  16. This little module might be of use to somebody - it sends 16-bit values to an external serial device, as four ascii hexidecimal digits (eg "12AB"), with new lines and carriage returns. The sample design send the settings of the 16 slide switches every time the center button is pressed.
  17. Hi, I have been working on a PMOD TFT LCD that can be used to play video directly from the FPGA using only two PMODs. I designed the hardware a couple of years ago but recently I had to do a project where I needed to use the Vivado block diagram interface. I thought it was pretty cool how fast it was to put a design together so I went about making an IP Core that controlled the PMOD. It has an AXI Lite interface used to initialize the LCD and then a AXI Stream interface that can be connected directly to a VDMA core. I ended up making three different demos including the following: Using the Microblaze to write directly to the screen. I wrote another core that behaves like a console output that will write directly to the screen for you so the MCU doesn't need to write the console stuff to the screen. I streamed video. Unfortunately this was harder than I expected and had to use the Pynq board instead. Here's a video of it working. I wrote a project page on with more details I was thinking of trying to sell the boards but I didn't know if there would be any interest. Dave
  18. So, I am starting to get these errors during the Place & Route phase WARNING:Par:288 - The signal kbd<0>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<1>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<2>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<3>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<4>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<5>_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal kbd<6>_IBUF has no load. PAR will not attempt to route this signal. it only started when I added the enb register. It really makes no sense. `timescale 1ns / 1ps module Trigger(trig,trigb,kbd); output trig; output trigb; input[7:0] kbd; reg trigb; reg trig; reg enb; always begin trigb = kbd[7]; end always @* begin case(kbd) 0: begin enb = 0; trig = 0; end 254: begin // line 0 trig = 0; enb = 0; // kbdphase = 1; end 253: begin // line 1 trig = 0; enb =0; end 251: begin // line 2 trig = 0; enb =0; end 247: begin // line 3 trig = 0; enb =0; end 239: begin // line 4 trig = 0; enb =0; end 223: begin // line 5 trig = 0; enb =0; end 191: begin // line 6 trig = 0; enb = 1; end 127: begin // line 7 if (enb) begin trig = 1; enb = 0; end else begin enb = 0; trig = 0; end end default begin enb = 0; trig = 0; end endcase; end endmodule The idea behind this is that the C64's Keyboard has 8 Column lines that get strobed individually. The row lines will return the keys that are pressed on that column (not implemented). Right now it just throws a line (TRIG) when a line goes high. The problem is that the line 7 does not behave like exactly like the others. It can actually go low for other reasons but never after line 6. So I thought to put up an enable pin to be turned on during line 6 period and then this will let line 7 know it can do its job and it can set the enable register go low again. Anyways, the ISE is giving me a terrible time. Also I can't understand why it requires me to set the enb line low on practically every single part of the case statement... otherwise I get it complaining about a possible latch. Do you all notice anything I am doing wrong? Thanks a lot for any help you can provide.
  19. FlyMario

    FPGA Clock

    I am learning how to program a FPGA (spartan) lately. The language I am using is Verilog which is not really important to this question. I have the FPGA connected to my Commodore 64 via Logic Level Converters. And I am having lot of success. I am reading 8 lines from the Keyboard port looking. My verilog is simply looking for a matching value on those lines. No problems at all. But I am curious, how is the logic managing to work when I have not really set up a clocking line. Is the FPGA using main clock to trigger events to move on in the FPGA. For instance, if you have a blocking statement it would seem that in order to get past that block, there must be some clock checking the incoming value before the logic can continue. Is this true? Or am I missing something. Is there a clock in the fpga that is pushing the logic along? Flymario
  20. mihai5

    IDS on zedboard

    Hi everyone, I want to implement an intrustion detection system on zedboard. I want to use PL for string matching and PS to handle the interrupts on possitive detection. Being a beginner in this area(FPGA + networking) I would like to know if this is possible and any informations or any type of instructions or steps that can help me is tremendously appreciated.
  21. Prompted by another thread here ( ), I've been experimenting the the Dynamic Reconfiguration Port on the Artix-7 MMCM You can find the code and constraints for the Basys3 here: It might be of interest to somebody (e.g. to change a VGA clock frequency dynamically).
  22. Hello, I'm building this filter, generating a .COE file in Matlab, which I use in the FIR compiler IP. Here are two screenshots of the settings. Do you know if the difference between the two pictures, in terms of magnitude, are just a displaying fact or if there is a real amlpification involved by the FIR compiler ? If it's the case, do you know how to fix it to generate the same filter as I designed in Matlab, so without gain ? Kind regards, Yannick
  23. I was attempting to use the Board tab within a block design in Vivado 2016.4 to connect some of the board interfaces on a Nexys Video FPGA board. In particular, the HDMI In component goes and instantiates both the TMDS signals in, as well as the DDC signals out, and Vivado marks the HDMI In component as connected. However, when I go to synthesize or elaborate the design, I get a bunch of messages telling me that top-level ports have not been assigned to an IO, and if I open up the I/O Port window, I can see that there's no package pin assigned to the HDMI ports. The only package pins that seem to be assigned are the board clock and reset. I don't think it's a problem with the board files, since I can clearly see from the Board tab that the interfaces are there. And the tool did know which pins were connected to clock and reset. My concern is that it looks like the iostandard and loc properties in part0_pins.xml aren't being understood by Vivado, since the ports ended up unconnected and some have the wrong IO standard (see screenshots). I would upload the project file, but it looks like its too big for the forum by a few MBs, so I posted some screenshots instead, as well as the board files. Does anyone know what could be wrong? I know a UCF file with LOC constraints will work, but that defeats the whole point of the board files that include pin definitions. mig.prj board.xml part0_pins.xml preset.xml
  24. Hello, I'm currently trying to implement a simple low-pass filter using the FIR Compiler available in the IP catalog. My design is very basic, I've generated a sine wave using the DDS IP : * Configuration Options : Phase generator and SIN COS LUT * System clock : 100 MHz * Mode of operation : Standard * Output frequency : 1.2 MHz * Output width : 8 Bits I want now to apply a low-pass filter and to see how is it going in simulation, using Analog waveform style. To generate the coefficients, I am using Matlab and the filterDesigner. Here are the specifications : * Lowpass, FIR (Equiripple) * Fs : 2.7 MHz * Fpass : 1.3 MHz * Fstop : 1.35 MHz * Apass : 1 dB * Astop :40 dB Then, I generate a .COE file which I use in the FIR compiler. I specify these options : * Filter type : Single rate * Input sampling frequency : 2.7 MHz * Clock frequency : 100 MHz * Coefficient type : signed, on 16 bits * Coefficient structure : Inferred * Input data type : Signed, on 8 bits * Output rounding mode : Full precision The screenshot shows what I obtain and it seems that it is not working very well. Does anybody can explain me what is going on ? Do I make some mistakes when I am setting up the filter ? Thank you very much for your help !
  25. I bought a Spartan-3E 500K Starter Board from ebay. The board looks new to me. When I plugged in the power supply, only 1 (red or power) of 3 LEDs (red, yellow and green) was on. The remaining 2 LEDs were off. In addition, there was no display on LCD. What's going on with my board? Is it a bad board?