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Found 311 results

  1. Hi, It took me a while to get the 7-series OSERDESE2 to simulate and work correctly. If anybody is having similar pain I've put my 10:1 serializer code up on my Wiki. The secret is to use the reset, and then assert CE. http://hamsterworks.co.nz/mediawiki/index.php/OSERDESE2 If you have trouble getting the clocks to work, both 'clk' and 'clk_x5' have to be driven from the same MMCM or a few other possible combinations. It would pay to read the manual (http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf) very carefully, but be careful of a few errors in the documentation...
  2. yasirshah

    Vmodcam resolution

    I am using Digilent Atlys board and Vmodcam in a project. Vmodcam have 1600*1200 maximum resolution. it can be used with 640*480 resolution. I want to know that what is the minimum resolution of Vmodcam. Can it be used for 300*200 resolution?
  3. I've finally got my PmodMIC3 out of it's back and have it up and running. http://hamsterworks.co.nz/mediawiki/index.php/Digital_Microphone It's pretty interesting how the MEMS microphones work - it seems to be much like this, but at audio frequencies:
  4. sudhir

    Basys 2 Board not working

    Just bought a brand new Basys 2 from an authorized dealer in India. I connect the Basys 2 and load Adept and get an " "Initialization Failed. Check connections and try again". After which I get "Found device ID: ffffffff Initialization Failed." in the Adept Screen! Any idea what to do? I'v bought many boards from Digilent and this is the first time I'v seen this error. Someone PLEASE HELP! PS: It's not been even a month since I bought this board. Do we have any warranty?
  5. Hello, I am new to FPGA programming so I am trying to do the Basys 3 Getting Started tutorial from the wiki. However, when I try to open a hardware target in Vivado, I get the error: [Labtoolstcl 44-26] No hardware targets exist on the server [TCP:localhost:3121] Check to make sure the cable targets connected to this machine are properly connected and powered up, then use the disconnect_hw_server and connect_hw_server commands to re-register the hardware targets. The cables seem to be properly connected and the board is on. I followed the commands above and get the same error. I uninstalled and installed the digilent drivers several times but I still get the error. I downloaded Adept and the Basys 3 also doesn't show up under the device manager. My computer must not be detecting it but I'm not sure why. Thanks.
  6. Hi, We have developed a nexys4 firmware for our pixel readout chip DAQ. We are using hardware TCP/UDP module (SiTcp) to communicate with board. You can find the project here: https://github.com/SiLab-Bonn/pyBAR/tree/development/firmware/nexys4 We extensively make use of basil framework: https://github.com/SiLab-Bonn/basil /Tomasz
  7. I'm trying to use the Analog Discovery logic analyzer with an Intel Edison. The Edison has 1.8V I/O. This does not reliably trigger the LVCMOS33 inputs on the FPGA inside the Analog Discovery. I think it might be possible to reconfigure the FPGA as LVCMOS18 input with a software option and the appropriate FPGA configuration. So I would like to request this feature in a future Waveforms3 update. Thanks!
  8. Hi! I'm really excited about a project I'm working on - it nearly realizes a childhood dream of building a computer for real-time exploring of Mandelbrot Fractals.(yes, sad but true - I did calculate fractals on a VIC20) If you have a Basys3, have a look and tell me what you think. http://hamsterworks.co.nz/mediawiki/index.php/Mandelbrot_NG Resource usage is pretty good - nearly gobbled them all! I'm still polishing it before I put the source on my Wiki, but it features a 1560 stage, 250MHz pipeline to calculate each pixel on the fly - works out to 33 billion 17x17 multiplications per second, approximately half the FPGA's rated peak performance.
  9. hi i am trying to cummunicate to pc with fpga board. i am using atlys board of digilent company in which spartan-6 (xc6slx45csg324c) is connected to marevell 88E1111 phy chip. my frame is:- constant udp_frameA :frame60:= (x"FF",x"FF",x"FF",x"FF", -- mac dest x"FF",x"FF",x"00",x"00", x"00",x"04",x"14",x"13", -- mac src x"08",x"00",x"45",x"00", -- IP header x"00",x"2E",x"00",x"00", x"00",x"00",x"40",x"11", x"7A",x"C0",x"00",x"00", -- IP src x"00",x"00",x"FF",x"FF", -- IP dest x"FF",x"FF",x"00",x"00", -- port src x"50",x"DA",x"00",x"12", -- port dest + len x"00",x"00",x"41",x"41", -- checksum udp + data "A" x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41"); and i am getting same frame on simulation and chipScope but i am not getting this frame in proper order on Wireshark. Wireshark result attached with it. please find this attachment. please respond me as soon as possible.
  10. Hello everyone, I am interested in purchasing a simple developing board to develop (more or less) an RFID emulator. Basically the chip only has to drive an RF SPDT connected to one of its pins based on some logic that I will implement. Initially I will just just need to have some data (2-3 kB) saved in memory that I will encode using Hamming(16,10) and send it to the SPDT with a rate of 5Mbits/sec. I am fairly new to FPGA developmen and although I have written some VHDL (a simulation of the tomasulo algorithm, a simple ALU during my undergrad), I consider myself a complete newbie. Do you guys have a recommendation for an FPGA dev kit with a simple programming interface(e.g. USB), preferably compatible with linux AND windows machines? I suspect that the logic that I am going to download will not occupy too much space so I don't need a large in terms of LUT's FPGa but I might need to do some signal processing so I would prefer something with the "newest technology" (talking newbish here). Moreover, I am very concerned about the toolchain, I have used webkit in the past and, well I will just say that I don't expect much from the newer versions. Is there anything better or do you have any suggestions. I am not really concerned about paying for a 1000$ license if I can save a month of bug/driver/compatibility nonsense. I also want to buy PC and I am looking for something that will be able to handle all the driver/connectivity/performance constrains that are associated with the toolchain. I have payed for a 1000$ Dell once with a fake PCIe4 port and I don't want to have the same experience again. see here Thank you very much in advance Lefteris
  11. cfelton

    Atlys board discontinued

    It came to our attention the Atlys is discontinued. Is there a suggested upgrade board (i.e a replacement for the Atlys)? Regards, Chris
  12. hogan

    adi i2s driver err ?

    I use zybo_base_system on Vivado 2014.4 installed to a 64-bit Win7 system. ALSA driver is initialized, and some 24/96 WAV file playback(by using "aplay") through my USB Audio class2.0 adaptor is no problem. But unfortunately, I've never been able to use "axi_i2s_adi" core via ALSA. I want to output I2S signal from some PMOD connector. Boot message is shown bellow. ######################################################################################################### U-Boot 2014.01-00005-gc29bed9 (Apr 24 2015 - 15:10:05) I2C: ready Memory: ECC disabled DRAM: 512 MiB MMC: zynq_sdhci: 0 SF: Detected S25FL128S_64K with page size 256 Bytes, erase size 64 KiB, total 16 MiB *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: Gem.e000b000 Hit any key to stop autoboot: 0 Device: zynq_sdhci Manufacturer ID: 27 OEM: 5048 Name: SD16G Tran Speed: 50000000 Rd Block Len: 512 SD version 3.0 High Capacity: Yes Capacity: 14.5 GiB Bus Width: 4-bit reading uEnv.txt ** Unable to read file uEnv.txt ** Copying Linux from SD to RAM... reading uImage 3519960 bytes read in 330 ms (10.2 MiB/s) reading devicetree.dtb 10014 bytes read in 16 ms (610.4 KiB/s) reading uramdisk.image.gz 3333361 bytes read in 297 ms (10.7 MiB/s) ## Booting kernel from Legacy Image at 03000000 ... Image Name: Linux-3.18.0-xilinx-46106-g3913e Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 3519896 Bytes = 3.4 MiB Load Address: 00008000 Entry Point: 00008000 Verifying Checksum ... OK ## Loading init Ramdisk from Legacy Image at 02000000 ... Image Name: Image Type: ARM Linux RAMDisk Image (gzip compressed) Data Size: 3333297 Bytes = 3.2 MiB Load Address: 00000000 Entry Point: 00000000 Verifying Checksum ... OK ## Flattened Device Tree blob at 02a00000 Booting using the fdt blob at 0x2a00000 Loading Kernel Image ... OK Loading Ramdisk to 1f801000, end 1fb2ecb1 ... OK Loading Device Tree to 1f7fb000, end 1f80071d ... OK Starting kernel ... Booting Linux on physical CPU 0x0 Linux version 3.18.0-xilinx-46106-g3913e72-dirty (root@localhost.localdomain) (gcc version 4.8.3 20140320 (prerelease) (Sourcery CodeBench Lite 2014.05-23) ) #1 SMP PREEMPT Thu May 7 11:42:01 JST 2015 CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=18c5387d CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache Machine model: Xilinx Zynq cma: Reserved 16 MiB at 0x1e400000 Memory policy: Data cache writealloc PERCPU: Embedded 10 pages/cpu @5fbd2000 s8768 r8192 d24000 u40960 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 130048 Kernel command line: console=ttyPS0,115200 root=/dev/ram rw earlyprintk PID hash table entries: 2048 (order: 1, 8192 bytes) Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) Memory: 492808K/524288K available (4756K kernel code, 272K rwdata, 1656K rodata, 216K init, 220K bss, 31480K reserved, 0K highmem) Virtual kernel memory layout: vector : 0xffff0000 - 0xffff1000 ( 4 kB) fixmap : 0xffc00000 - 0xffe00000 (2048 kB) vmalloc : 0x60800000 - 0xff000000 (2536 MB) lowmem : 0x40000000 - 0x60000000 ( 512 MB) pkmap : 0x3fe00000 - 0x40000000 ( 2 MB) modules : 0x3f000000 - 0x3fe00000 ( 14 MB) .text : 0x40008000 - 0x4064b2f0 (6413 kB) .init : 0x4064c000 - 0x40682000 ( 216 kB) .data : 0x40682000 - 0x406c62a0 ( 273 kB) .bss : 0x406c62a0 - 0x406fd2b8 ( 221 kB) Preemptible hierarchical RCU implementation. Dump stacks of tasks blocking RCU-preempt GP. RCU restricting CPUs from NR_CPUS=4 to nr_cpu_ids=2. RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 NR_IRQS:16 nr_irqs:16 16 L2C-310 erratum 769419 enabled L2C-310 enabling early BRESP for Cortex-A9 L2C-310 full line of zeros enabled for Cortex-A9 L2C-310 ID prefetch enabled, offset 1 lines L2C-310 dynamic clock gating enabled, standby mode enabled L2C-310 cache controller enabled, 8 ways, 512 kB L2C-310: CACHE_ID 0x410000c8, AUX_CTRL 0x76360001 ps7-slcr mapped to 60804000 zynq_clock_init: clkc starts at 60804100 Zynq clock init sched_clock: 64 bits at 325MHz, resolution 3ns, wraps every 3383112499200ns ps7-ttc #0 at 60806000, irq=43 Console: colour dummy device 80x30 Calibrating delay loop... 1292.69 BogoMIPS (lpj=6463488) pid_max: default: 32768 minimum: 301 Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) CPU: Testing write buffer coherency: ok CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 Setting up static identity map for 0x47f168 - 0x47f1c0 CPU1: Booted secondary processor CPU1: thread -1, cpu 1, socket 0, mpidr 80000001 Brought up 2 CPUs SMP: Total of 2 processors activated. CPU: All CPU(s) started in SVC mode. devtmpfs: initialized VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 regulator-dummy: no parameters NET: Registered protocol family 16 DMA: preallocated 256 KiB pool for atomic coherent allocations cpuidle: using governor ladder cpuidle: using governor menu hw-breakpoint: found 5 (+1 reserved) breakpoint and 1 watchpoint registers. hw-breakpoint: maximum watchpoint size is 4 bytes. zynq-ocm f800c000.ps7-ocmc: ZYNQ OCM pool: 256 KiB @ 0x60880000 GPIO IRQ not connected XGpio: /amba@0/gpio@41200000: registered, base is 902 GPIO IRQ not connected XGpio: /amba@0/gpio@41220000: registered, base is 898 vgaarb: loaded SCSI subsystem initialized usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb media: Linux media interface: v0.10 Linux video capture interface: v2.00 pps_core: LinuxPPS API ver. 1 registered pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it> PTP clock support registered EDAC MC: Ver: 3.0.0 Advanced Linux Sound Architecture Driver Initialized. Switched to clocksource arm_global_timer NET: Registered protocol family 2 TCP established hash table entries: 4096 (order: 2, 16384 bytes) TCP bind hash table entries: 4096 (order: 3, 32768 bytes) TCP: Hash tables configured (established 4096 bind 4096) TCP: reno registered UDP hash table entries: 256 (order: 1, 8192 bytes) UDP-Lite hash table entries: 256 (order: 1, 8192 bytes) NET: Registered protocol family 1 RPC: Registered named UNIX socket transport module. RPC: Registered udp transport module. RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. Trying to unpack rootfs image as initramfs... rootfs image is not initramfs (no cpio magic); looks like an initrd Freeing initrd memory: 3256K (5f801000 - 5fb2f000) hw perfevents: enabled with armv7_cortex_a9 PMU driver, 7 counters available futex hash table entries: 512 (order: 3, 32768 bytes) jffs2: version 2.2. (NAND) (SUMMARY) c 2001-2006 Red Hat, Inc. msgmni has been set to 1000 io scheduler noop registered io scheduler deadline registered io scheduler cfq registered (default) dma-pl330 f8003000.ps7-dma: Loaded driver for PL330 DMAC-241330 dma-pl330 f8003000.ps7-dma: DBUFF-128x8bytes Num_Chans-8 Num_Peri-4 Num_Events-16 xuartps e0001000.serial: ttyPS0 at MMIO 0xe0001000 (irq = 82, base_baud = 3125000) is a xuartps console [ttyPS0] enabled xdevcfg f8007000.ps7-dev-cfg: ioremap 0xf8007000 to 6081c000 [drm] Initialized drm 1.1.0 20060810 brd: module loaded loop: module loaded CAN device driver interface e1000e: Intel(R) PRO/1000 Network Driver - 2.3.2-k e1000e: Copyright(c) 1999 - 2014 Intel Corporation. libphy: XEMACPS mii bus: probed xemacps e000b000.ps7-ethernet: pdev->id -1, baseaddr 0xe000b000, irq 54 ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver ehci-pci: EHCI PCI platform driver ULPI transceiver vendor/product ID 0x0424/0x0007 Found SMSC USB3320 ULPI transceiver. ULPI integrity check: passed. zynq-ehci zynq-ehci.0: Xilinx Zynq USB EHCI Host Controller zynq-ehci zynq-ehci.0: new USB bus registered, assigned bus number 1 zynq-ehci zynq-ehci.0: irq 53, io mem 0x00000000 zynq-ehci zynq-ehci.0: USB 2.0 started, EHCI 1.00 hub 1-0:1.0: USB hub found hub 1-0:1.0: 1 port detected usbcore: registered new interface driver usb-storage mousedev: PS/2 mouse device common for all mice i2c /dev entries driver cdns-i2c e0004000.ps7-i2c: 400 kHz mmio e0004000 irq 57 Xilinx Zynq CpuIdle Driver started sdhci: Secure Digital Host Controller Interface driver sdhci: Copyright(c) Pierre Ossman sdhci-pltfm: SDHCI platform and OF driver helper sdhci-arasan e0100000.ps7-sdio: No vmmc regulator found sdhci-arasan e0100000.ps7-sdio: No vqmmc regulator found mmc0: SDHCI controller on e0100000.ps7-sdio [e0100000.ps7-sdio] using ADMA ledtrig-cpu: registered to indicate activity on CPUs usbcore: registered new interface driver usbhid usbhid: USB HID core driver usbcore: registered new interface driver snd-usb-audio axi-i2s: probe of 43c20000.axi-i2s-adi failed with error -2 TCP: cubic registered NET: Registered protocol family 17 can: controller area network core (rev 20120528 abi 9) NET: Registered protocol family 29 can: raw protocol (rev 20120528) can: broadcast manager protocol (rev 20120528 t) can: netlink gateway (rev 20130117) max_hops=1 zynq_pm_ioremap: no compatible node found for 'xlnx,zynq-ddrc-a05' zynq_pm_late_init: Unable to map DDRC IO memory. Registering SWP/SWPB emulation handler drivers/rtc/hctosys.c: unable to open rtc device (rtc0) ALSA device list: No soundcards found. RAMDISK: gzip image found at block 0 mmc0: new high speed SDHC card at address 0007 mmcblk0: mmc0:0007 SD16G 14.4 GiB mmcblk0: p1 p2 EXT2-fs (ram0): warning: mounting unchecked fs, running e2fsck is recommended VFS: Mounted root (ext2 filesystem) on device 1:0. devtmpfs: mounted Freeing unused kernel memory: 216K (4064c000 - 40682000) Starting rcS... ++ Mounting filesystem ++ Setting up mdev ++ Starting telnet daemon ++ Starting http daemon ++ Starting ftp daemon ++ Starting dropbear (ssh) daemon random: dropbear urandom read with 1 bits of entropy available rcS Complete ################################################################################################## I don't understand the meaning of "axi-i2s: probe of 43c20000.axi-i2s-adi failed with error -2" . Could you teach me what to do next? Device tree source about adi_i2s is... axi_i2s_adi_0: axi-i2s-adi@43c20000 { compatible = "adi,axi-i2s-1.00.a"; reg = <0x43c20000 0x1000>; xlnx,bclk-pol = <0x0>; xlnx,dma-type = <0x1>; xlnx,has-rx = <0x1>; xlnx,has-tx = <0x1>; xlnx,lrclk-pol = <0x0>; xlnx,num-ch = <0x1>; xlnx,s00-axi-addr-width = <0x6>; xlnx,s00-axi-data-width = <0x20>; xlnx,slot-width = <0x18>; } ; .config ################################################################################################ CONFIG_SOUND=y # CONFIG_SOUND_OSS_CORE is not set CONFIG_SND=y CONFIG_SND_TIMER=y CONFIG_SND_PCM=y CONFIG_SND_DMAENGINE_PCM=y CONFIG_SND_HWDEP=y CONFIG_SND_RAWMIDI=y CONFIG_SND_COMPRESS_OFFLOAD=y CONFIG_SND_JACK=y # CONFIG_SND_SEQUENCER is not set # CONFIG_SND_MIXER_OSS is not set # CONFIG_SND_PCM_OSS is not set # CONFIG_SND_HRTIMER is not set # CONFIG_SND_DYNAMIC_MINORS is not set CONFIG_SND_SUPPORT_OLD_API=y CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_VERBOSE_PRINTK is not set # CONFIG_SND_DEBUG is not set # CONFIG_SND_RAWMIDI_SEQ is not set # CONFIG_SND_OPL3_LIB_SEQ is not set # CONFIG_SND_OPL4_LIB_SEQ is not set # CONFIG_SND_SBAWE_SEQ is not set # CONFIG_SND_EMU10K1_SEQ is not set CONFIG_SND_DRIVERS=y # CONFIG_SND_DUMMY is not set # CONFIG_SND_ALOOP is not set # CONFIG_SND_MTPAV is not set # CONFIG_SND_SERIAL_U16550 is not set # CONFIG_SND_MPU401 is not set CONFIG_SND_PCI=y # CONFIG_SND_AD1889 is not set # CONFIG_SND_ALS300 is not set # CONFIG_SND_ALI5451 is not set # CONFIG_SND_ATIIXP is not set # CONFIG_SND_ATIIXP_MODEM is not set # CONFIG_SND_AU8810 is not set # CONFIG_SND_AU8820 is not set # CONFIG_SND_AU8830 is not set # CONFIG_SND_AW2 is not set # CONFIG_SND_AZT3328 is not set # CONFIG_SND_BT87X is not set # CONFIG_SND_CA0106 is not set # CONFIG_SND_CMIPCI is not set # CONFIG_SND_OXYGEN is not set # CONFIG_SND_CS4281 is not set # CONFIG_SND_CS46XX is not set # CONFIG_SND_CTXFI is not set # CONFIG_SND_DARLA20 is not set # CONFIG_SND_GINA20 is not set # CONFIG_SND_LAYLA20 is not set # CONFIG_SND_DARLA24 is not set # CONFIG_SND_GINA24 is not set # CONFIG_SND_LAYLA24 is not set # CONFIG_SND_MONA is not set # CONFIG_SND_MIA is not set # CONFIG_SND_ECHO3G is not set # CONFIG_SND_INDIGO is not set # CONFIG_SND_INDIGOIO is not set # CONFIG_SND_INDIGODJ is not set # CONFIG_SND_INDIGOIOX is not set # CONFIG_SND_INDIGODJX is not set # CONFIG_SND_EMU10K1 is not set # CONFIG_SND_EMU10K1X is not set # CONFIG_SND_ENS1370 is not set # CONFIG_SND_ENS1371 is not set # CONFIG_SND_ES1938 is not set # CONFIG_SND_ES1968 is not set # CONFIG_SND_FM801 is not set # CONFIG_SND_HDSP is not set # CONFIG_SND_HDSPM is not set # CONFIG_SND_ICE1712 is not set # CONFIG_SND_ICE1724 is not set # CONFIG_SND_INTEL8X0 is not set # CONFIG_SND_INTEL8X0M is not set # CONFIG_SND_KORG1212 is not set # CONFIG_SND_LOLA is not set # CONFIG_SND_MAESTRO3 is not set # CONFIG_SND_MIXART is not set # CONFIG_SND_NM256 is not set # CONFIG_SND_PCXHR is not set # CONFIG_SND_RIPTIDE is not set # CONFIG_SND_RME32 is not set # CONFIG_SND_RME96 is not set # CONFIG_SND_RME9652 is not set # CONFIG_SND_SONICVIBES is not set # CONFIG_SND_TRIDENT is not set # CONFIG_SND_VIA82XX is not set # CONFIG_SND_VIA82XX_MODEM is not set # CONFIG_SND_VIRTUOSO is not set # CONFIG_SND_VX222 is not set # CONFIG_SND_YMFPCI is not set # # HD-Audio # # CONFIG_SND_HDA_INTEL is not set CONFIG_SND_ARM=y # CONFIG_SND_ARMAACI is not set CONFIG_SND_SPI=y CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=y # CONFIG_SND_USB_UA101 is not set # CONFIG_SND_USB_CAIAQ is not set # CONFIG_SND_USB_6FIRE is not set # CONFIG_SND_USB_HIFACE is not set # CONFIG_SND_BCD2000 is not set CONFIG_SND_SOC=y CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y CONFIG_SND_SOC_ADI=y CONFIG_SND_SOC_ADI_AXI_I2S=y CONFIG_SND_SOC_ADI_AXI_SPDIF=y CONFIG_SND_ATMEL_SOC=y # CONFIG_SND_DESIGNWARE_I2S is not set # # SoC Audio for Freescale CPUs # # # Common SoC Audio options for Freescale CPUs: # # CONFIG_SND_SOC_FSL_ASRC is not set # CONFIG_SND_SOC_FSL_SAI is not set # CONFIG_SND_SOC_FSL_SSI is not set # CONFIG_SND_SOC_FSL_SPDIF is not set # CONFIG_SND_SOC_FSL_ESAI is not set # CONFIG_SND_SOC_IMX_AUDMUX is not set CONFIG_SND_SOC_XILINX_DP=y CONFIG_SND_SOC_I2C_AND_SPI=y # # CODEC drivers # # CONFIG_SND_SOC_ADAU1701 is not set # CONFIG_SND_SOC_AK4104 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_ALC5623 is not set # CONFIG_SND_SOC_CS35L32 is not set # CONFIG_SND_SOC_CS42L52 is not set # CONFIG_SND_SOC_CS42L56 is not set # CONFIG_SND_SOC_CS42L73 is not set # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set # CONFIG_SND_SOC_CS4271 is not set # CONFIG_SND_SOC_CS42XX8_I2C is not set # CONFIG_SND_SOC_HDMI_CODEC is not set # CONFIG_SND_SOC_ES8328 is not set # CONFIG_SND_SOC_PCM1681 is not set # CONFIG_SND_SOC_PCM1792A is not set # CONFIG_SND_SOC_PCM512x_I2C is not set # CONFIG_SND_SOC_PCM512x_SPI is not set # CONFIG_SND_SOC_SGTL5000 is not set # CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set # CONFIG_SND_SOC_SPDIF is not set # CONFIG_SND_SOC_SSM2602_SPI is not set # CONFIG_SND_SOC_SSM2602_I2C is not set # CONFIG_SND_SOC_SSM4567 is not set # CONFIG_SND_SOC_STA350 is not set # CONFIG_SND_SOC_TAS2552 is not set # CONFIG_SND_SOC_TAS5086 is not set # CONFIG_SND_SOC_TLV320AIC31XX is not set # CONFIG_SND_SOC_TLV320AIC3X is not set # CONFIG_SND_SOC_WM8510 is not set # CONFIG_SND_SOC_WM8523 is not set # CONFIG_SND_SOC_WM8580 is not set # CONFIG_SND_SOC_WM8711 is not set # CONFIG_SND_SOC_WM8728 is not set # CONFIG_SND_SOC_WM8731 is not set # CONFIG_SND_SOC_WM8737 is not set # CONFIG_SND_SOC_WM8741 is not set # CONFIG_SND_SOC_WM8750 is not set # CONFIG_SND_SOC_WM8753 is not set # CONFIG_SND_SOC_WM8770 is not set # CONFIG_SND_SOC_WM8776 is not set # CONFIG_SND_SOC_WM8804 is not set # CONFIG_SND_SOC_WM8903 is not set # CONFIG_SND_SOC_WM8962 is not set # CONFIG_SND_SOC_WM8978 is not set # CONFIG_SND_SOC_TPA6130A2 is not set CONFIG_SND_SIMPLE_CARD=y # CONFIG_SOUND_PRIME is not set ################################################################################################
  13. hi i am trying to cummunicate to pc with fpga board. i am using atlys board of digilent company in which spartan-6 (xc6slx45csg324c) is connected to marevell 88E1111 phy chip.In this project i am facing the problem to getting the mac address of board (phy chip) to send the arp frame and udp frame.because i am manually framming the udp and arp frame fr in my code for which i need source mac address i.e mac address of fpga board (or marvell phy chip). please respond me as soon as possible. constant udp_frameA :frame60:= (x"FF",x"FF",x"FF",x"FF", -- mac dest x"FF",x"FF",x"00",x"00", x"00",x"04",x"14",x"13", -- i want to know this source mac address. x"08",x"00",x"45",x"00", -- IP header x"00",x"2E",x"00",x"00", x"00",x"00",x"40",x"11", x"7A",x"C0",x"00",x"00", -- IP src x"00",x"00",x"FF",x"FF", -- IP dest x"FF",x"FF",x"00",x"00", -- port src x"50",x"DA",x"00",x"12", -- port dest + len x"00",x"00",x"41",x"41", -- checksum udp + data "A" x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41", x"41",x"41",x"41",x"41");
  14. Hi, Somebody was after a way to send the input state of FPGA pins through to a host/PC for logging, so I knocked a quick hack up for them. http://hamsterworks....ex.php/Log_Pins It logs 11 pins as an ASCII string of ones and zeros, followed by a NL and CR, at 9600 baud using RS232, but that can be tweaked. It only sends an update when the state of the input changes. On the development board I'm using it is to an on-board USB virtual serial port, but you could also use a USB to TTL RS232 adapter. Maybe somebody may be able to make use of it as a debugging interface,..
  15. logansam

    FPGA SNES

    I just found this project using the original Nexys FPGA for a SNES emulator! Check out the whole project at http://danstrother.com/fpga-nes/
  16. logansam

    Nexys FPGA board

    From the album: Nexys FPGA SNES

    http://danstrother.com/fpga-nes/
  17. logansam

    FPGA NES

    From the album: Nexys FPGA SNES

    http://danstrother.com/fpga-nes/
  18. Hi all, I recently acquired a Basys3 board and read that it was designed to work exclusively with Vivado. I want to do some projects using Labview and have found that other boards, such as the Basys2 and the Nexys series are compatible with it and documentation is provided as to how to interface the boards with LV. I am just wondering if it is also possible to interface the Basys3 board with Labview. Thank you
  19. A customer asked the following question. I am looking to perform some research using DDR DRAM chips. I would like to dynamically adjust the power to just the DRAM chip while running test programs from a FPGA/processor. This means that I need a board with both a soft DDR controller core (so I can manipulate the refresh rate) and, at the same time, control just the DRAM voltage (I don't want to mess with the FPGA's voltage). Do you sell any boards that meet both of these criteria? I am not opposed to de-soldering capacitors and powering the DRAM from the exposed pads. Here is the recommendation. You can look at the Atlys.
  20. Hello All, I have attached serially 4 Kintex-7 FPGA to program them in Serial JTAG configuration , All configuration works with 3 FPGA when we get to the 4 FPGA does not functioning at all. I have replaced the HS2 with Xilinx Cable 2-3 and evry things is working. It looks for me the issue of the FAN out of TMS and TCK signal . Is this is nothing to do with FTDI chip on the HS2 programmer whcih is going to limits the number of the FPGAs in the chain ? Any body have tested HS2 with this configuration ? any has solution for this ? BR Abbas
  21. Would it be possible to Open Source all or part of the Analog Discovery? Since the FPGA is programmed by the Digilent instrumentation software you are one step away from having a development board with many front end interfaces already on-board. The main thing I would be looking at is that it is open sourced enough (or documented enough) that I could use the Analog Discovery as a custom acquisition and/or control board for advanced testing or even prototyping. I know there is an API to access some functionality but could this be expanded to allow even more opportunities to customize the board?
  22. Hi! I'm just playing around with a low cost board that has HDMI input and output on it. It would make a very valuable but low cost addition on the next Basys and or Nexys model, given that analogue VGA displays are very pretty soon going to disappear. From the engineering point of view, Implementing DVI-D is a great way to experience the "pleasure" of high speed serial communications. From the student/hobbyist point of view, playing with camera modules and image processing algorithms with 8-bit or 12-bit VGA output is quite lame. From a purely aesthetic point of view, 24-bit colour images are so much nicer than low colour depths. From a cost point of view, it is one connector and maybe a few passives, and 8 pins on the FPGA. The only downside is that FPGAs don't have oodles of block RAM, and most low-cost high-capacity memory solutions (e.g. SDRAM) are relatively low bandwidth. This forces you have to process the data as it flows through the FPGA rather than bouncing frames in and out of memory of a frame buffer. Mike
  23. I am using the Electronics Explorer board, and I have a need to decode 3 different serial input lines, using a single CLK signal. Two of these serial input lines need to be decoded into 2 16-bit hex words (one 16-bit hex word for serial_in_1 and one 16-bit hex word for serial_in_2), triggered on both the rising and falling edges of CLK. The 3rd serial input line I need decoded into an 8-bit hex word, triggered on the falling edge of CLK. Is there any custom decoding functionality to perform something of this nature?
  24. I just got this up and running: http://youtu.be/dIAJrQxToCc It's a custom TFT LCD controller board using only two PMODs. The board controlling it is an FPGA devboard that communicates with the host computer using the FTDI's FT2232H in synchronous FIFO mode so that I can transfer data between the host and board at a rate of about 25MB/s using a simple protocol. I wrote a scripting tool that glues together wishbone cores to create an FPGA image using a simple configuration file. Editing configuration files are great but I thought it would be so much better if I could modify the FPGA image by using a GUI so I worked on an application that does that. Here is a screen shot of how I visually created the LCD controller. One of the big limitations of using USB 2.0 is the relatively large overhead to initiate a transaction, It's much faster if you send a large chunk of data. So instead of writing directly to the LCD controller I write to the SDRAM and then configure the LCD controller to read directly from the memory. This way I can write a new frame down to memory while the LCD controller is reading data out using a double buffer scheme (host writes to back, controller reads from front, then flip). The protocol to communicate with the FPGA is a really simple protocol abstracted away in Python to simply 'read' and 'write'. It was pretty cool to communicate with the FPGA using a python module but I thought it would be so much better if I could interface with an FPGA using a GUI. So I added a visual interface to communicate with it (That's what I was using in the video). If you're interested in the board here's the link: http://wiki.cospandesign.com/index.php?title=Dionysus the code to control the LCD is here: https://github.com/CospanDesign/nysa-verilog/tree/master/verilog/wishbone/slave/wb_nh_lcd The code is designed to be as generic as possible, so if you want to adapt it to your project it really just needs a wishbone bus but you can bypass Wishbone by just using the nh_lcd.v
  25. ricardo_lara_gomez

    Basys �

    I need a program to count the turns of a motor, could tell me I need?????????