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Found 337 results

  1. wheezs

    cmod 6 clock

    hey i cant finger out how to get the internal clock to use in projects
  2. C.Pallavi

    JTAG HS2

    Can we connect"JTAG HS2" cable to any VIrtex devices (Especially Virtex 2 and Virtex 4 FPGA).
  3. Evening, all. The code attempts to create a clock and synchronize it to sysclk. However, it fails timing analysis. `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Engineer: hamster, JUIXXXE ////////////////////////////////////////////////////////////////////////////////// module clk_div( input clk, output wire mclk, output wire bclk, output wire lrclk ); wire clkfb; reg [7:0] mclk_count = 0; MMCME2_BASE #( .BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW) .CLKFBOUT_MULT_F(7.0), // Multiply value for all CLKOUT (2.000-64.000). .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000). .CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). // CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128) .CLKOUT0_DIVIDE_F(57.0), // Divide amount for CLKOUT0 (1.000-128.000). .CLKOUT1_DIVIDE(14), .CLKOUT2_DIVIDE(14), .CLKOUT3_DIVIDE(14), .CLKOUT4_DIVIDE(14), .CLKOUT5_DIVIDE(14), .CLKOUT6_DIVIDE(14), // CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99). .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT3_DUTY_CYCLE(0.5), .CLKOUT4_DUTY_CYCLE(0.5), .CLKOUT5_DUTY_CYCLE(0.5), .CLKOUT6_DUTY_CYCLE(0.5), // CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000). .CLKOUT0_PHASE(0.0), .CLKOUT1_PHASE(0.0), .CLKOUT2_PHASE(0.0), .CLKOUT3_PHASE(0.0), .CLKOUT4_PHASE(0.0), .CLKOUT5_PHASE(0.0), .CLKOUT6_PHASE(0.0), .CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE) .DIVCLK_DIVIDE(1), // Master division value (1-106) .REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999). .STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked (FALSE, TRUE) ) MMCME2_BASE_inst ( // Clock Outputs: 1-bit (each) output: User configurable clock outputs .CLKOUT0(mclk), // 1-bit output: CLKOUT0 .CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0 .CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1 .CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1 .CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2 .CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2 .CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3 .CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3 .CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4 .CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5 .CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6 // Feedback Clocks: 1-bit (each) output: Clock feedback ports .CLKFBOUT(clkfb), // 1-bit output: Feedback clock .CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT // Status Ports: 1-bit (each) output: MMCM status ports .LOCKED(LOCKED), // 1-bit output: LOCK // Clock Inputs: 1-bit (each) input: Clock input .CLKIN1(clk), // 1-bit input: Clock // Control Ports: 1-bit (each) input: MMCM control ports .PWRDWN(1'b0), // 1-bit input: Power-down .RST(1'b0), // 1-bit input: Reset // Feedback Clocks: 1-bit (each) input: Clock feedback ports .CLKFBIN(clkfb) // 1-bit input: Feedback clock ); assign bclk = mclk_count[2]; // mclk / 8 assign lrclk = mclk_count[7]; // mclk / 256 reg mclk_last; [email protected](posedge(clk)) begin if(mclk & !mclk_last) mclk_count <= mclk_count + 1; mclk_last <= mclk; end endmodule From CLKOUT0 to mclk_count fails timing analysis. How can the code be restructured to avoid this?
  4. Greetings everybody, I recently purchased a Zybo (Zynq 7000 series application board), currently I am experimenting around with it a bit. This is the first time I am working with FPGAs, up to now I have only been working with other microcontrollers and cortex processors. While looking for reading material, I stumbled across this example, which shows how to create and use custom IP cores using Vivado. Since it is an official example from digilent and other examples worked without problems I though this one would be easy to follow, too. Problem is, it doesn't work. I am following each and every step exactly as shown in the pictures and described in the text. After successfully generating the bitstream (no warnings/errors) and exporting it I run the SDK. The C code there compiles, too, I program the FPGA and launch the compiled ELF using GDB on the Zynq. Here I first have to turn off the "Run ps7_init" and "Run ps7_post_config" checkboxes in the run configuration, otherwise the elf won't run on the Zynq. Now the ELF runs on the Zynq (or at least I hope so...), but nothing happens. Nothing at all. The LEDs are supposed to start pulsing, but they don't. Does anybody have similar experience with the given example? Or can anyone tell me what's wrong or how to find out? I'm greatful for any help you might have to offer. I currently am using Vivado 2015.4 (64 bit). Best regards, Daniel
  5. Hi all, I've recently bought an Arty board (Microblaze processor) and some Pmods (PmodDPOT, PmodDAs, PmodADs), which use SPI protocol. I've looked everywhere for an example on how to access the Pmod headers or just how to use Pmods with the Arty but I couldn't find anything (even on the reference wiki page for the Arty). I found a library for SPI on Xilinx SDK which is called Xspi but I also am not sure how to use it. Can anybody perhaps help me by giving me the basic steps on how to do this? I'm very new to FPGA, so any feedback or suggestions are welcome! Thanks Viv
  6. When I updated the FTDI VCP drivers( ,win7 X64 2.12.10), the ARTY onboard JTAG disappeared. And there are two USB-TO-COM on my computer. See attachment, please. Any suggestions?
  7. After finally finding a reason to start using my PMODamp3, I've created a little project that emits a very quiet 375Hz sine tone through an 8 Ohm speaker: It might be of use to anybody who want to use this PMOD in a design as a starting point.
  8. One thing I learnt today was that Vivado has a Virtual I/O IP block, that allows you to see the state of signals deep in your design. You can also use it to inject signals into your design too. I've added a little project to my Wiki which connects the switches and LEDs on the Basys3 to an instance of the Virtual I/O block. (Connecting to external I/O is not really the target end-use case - it would be perfect for monitoring status signals out of transceivers and memory controllers, or observing the state of misbehaving FSMs)
  9. I've been playing around with a sub-$10 6-axis gyro/acceleration/attitude sensor (from with my Basys3 (and my Raspberry Pi Zero). The sensor reports over RS232 at 115200 making it far easier to decode than with sensor that speak I2C. The short video at shows as the senor reads from -1G (approx 0xEFFF) to +1G ( approx 0x1000) as the sensor is rotated in the Y axis. Source can be found at
  10. Purely player vs player Tic Tac Toe, using one fpga. The game state is viewed through the VGA port, displaying the X's and O's in the grid on a connected monitor. User control is through the five push buttons, left/right/up/down control selection of a square, center confirms the selection. The project figures out when the game has ended and lights an RGB LED, and colors the winning line/s green. Originally created for the WSU Hackathon in February 2015, so I apologize if the source is a little convoluted, with the exception of most of the comments, the project was written in 24 hours.
  11. I am a sophomore in an electrical engineering program, and I would like to know what software I need for your starter kit/boards priced between 0 and $300. The boards and software must run on Windows 10 Pro and use VHDL. Note that Xilinx (Vivado) does not work on this computer; I don’t know why. As an FYI, my school uses the BASY 3, Artix-7 FPGA. Something similar to this would be appreciated. Thanks
  12. Hi, I've been using the constraints file from and from debugging the pins for JA seem to be wrong set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3] set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3] set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4] set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4] should really be set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja_p[3]set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L5N_T0_D07_14 Sch=ja_n[3] set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L4P_T0_D04_14 Sch=ja_p[4] set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L4N_T0_D05_14 Sch=ja_n[4] The low half seem to have the same problem too. The _p is connected to pin 1, 3, 7 or 9, and the _n is connected to pins 2,4,8 or 10 Looks like JB is the same too! Mike
  13. laltarac

    Basys2 PS/2 Keyboard

    Hello. Im working on a project that requires a ps2 keyboard to communicate to the Basys2 board. Does any one have any good links that might help me get started with this. Or, maybe would someone be able to post their Verilog code , if they've done it ? It would be much appreciated Thanks Liam
  14. Hi everyone! I have a Nexys 3 board which I have used to implement some designs. Now I am working on a ethernet controller implementation to perform high speed data transfer between a PC and a FPGA (point to point). The Nexys 3 includes a 10/100 PHY IC, but I have to go up to a gigabit PHY to achieve my goals. Is there any kind of peripheral module with a gigabit PHY that I could use with my Nexys 3? Thanks in advance (and sorry for my english :))
  15. I've got my 1080i real-time fractal design running on the Genesys2 board, and the source checked in at - I spent last night getting rid of the 8-bit colour look, using the HDMI's 24 bit range.It uses about 100k flip-flops, 150k LUTs and 640 DSP slices, so uses a large chunk of the FPGA. If anybody is after a reference point, the Kintex-7 FPGA on the Genesys2 added 0.670ns slack to the 225MHz design that just meets timing on he Artix-7. But I can't make can't make use of the extra speed as the calculations run at a multiple of the pixel clock. The logic was also fast enough that I could implement 20% of the multipliers using LUTs - allowing me to get to 255 iterations in real time.
  16. I realize I only know a tiny corner of all of VHDL. I know little about creating packages, libraries, other data types outside of 'std_logic' and 'signed', 'unsigned', 'integer' and 'natural', things like "a <= b after 10 ns;", string handling, file handling, structures, text I/O ..... the list goes on and on. Just how much of VHDL do you need to work with FPGAs? My guess is about 20% And once you get that far, is it worth learning more? And is Verilog the same? And does anybody have any recommended resources on more advanced VHDL?
  17. Hi, What is the clock rate of the ZYBO Zynq™-7000 Development Board? In particular I would like to know what would be the clock rate for the digital i/o that would be used for the fpga?
  18. Hey all! I am working on my senior design project at the moment and i'm planning on using an FPGA rather than microprocessor because I wanted something more hardware based since my team does not have a computer engineer. This is a huge learning experience for me seeing as my school did not cover HDL. I am trying to decide what FPGA would be able to handle everything that my project entails and was hoping for some help on that matter. My project is essentially a nutritional dispensing machine that will change the amount of each nutrient based on the users criteria. It will ask for at least three different criteria (sex,height,weight,amount of exercise, etc.) and use dietetics equations to output a personalized shake perfect for your body at that moment. It will have at least 5 ingredients that it will be controlling the amounts of. Multiple sensors will be handling ingredients levels and a pressure sensor will be used for the liquid, It will have to talk to a display to ask the user questions and then take in numerical inputs from the interface.Obviously it will be handling all of the equations and tables required in calculation. That is a quick description of the large things it will be handling, I understand a microprocessor could handle all of this but I want this to be a learning experience and FPGA's are something I want experience with. Both the zybo zynq, and the zedboard zynq have been suggested to me, however, even then there is a large price difference. Any help on this matter would be appreciated. Thanks!
  19. Hey everyone I have the Analog Discovery Module and I can generate the timing signals easily using the GUI which I really like. However I need more signals and a standalone system, as well as an SPI communication capability. Would any of the boards available on your site be compatible with the Waveforms software and have more IO as well as SPI? Thanks
  20. Hi, I am Jaeyoung, a Ph.D student in University of Texas at Austin. I am currently looking for a FPGA evaluation board that can generate/read 1.2V. I have searched a few FPGA boards, but these boards supports to 1.5V. Is there any appropriate board? I will use this board to generate 1.2V digital signal for inputs of my test chip and read-out an output of my test chip using the board. Any suggestion is appreciated. Best regards, Jaeyoung
  21. Hi all, I am creating a custom CPU on the Nexys 4 DDR. At 100 MHz system clock, it executes commands at about 20 MIPS on average. I used async SRAM in past, this was a piece of cake as the SRAM was always faster than my CPU. But now, being on the Nexys 4 DDR, I'd like to leverage the on board DDR RAM. Having a look at Mihaita Nagy's DDR to SRAM component (link: I was a bit surprised: On the reference page you can read, that an async. read operation of a single data word takes 210ns. Is this realistic or maybe a typo? 210ns means that the max read speed would be 4,76 MHz. This seems to slow to be true. So did I maybe get something wrong (I am a pretty new to DDR RAM topics therefore this might be the case). If I did not get it wrong: Just being curious: Why is it so slow? Are there faster ways to work with the DDR RAM? Thank you and best regards Mirko
  22. I've finally got a design for a valid DCC/EDID ROM that advertises support for HDMI input - see for more info. You can find it at and are more than welcome to include it in your designs if you want to.
  23. Mav7

    Starter FPGA?

    Which FPGA board would you recommend for a first time user?
  24. hamster


    If anybody is looking for source for an EDID ROM I've made one for 1080p, 1080i and 720p which seems to work OK.
  25. I'm working on a design for receving HDMI video and decided to write up my method for tuning the IDELAY and ISERDES settings to sync with the incoming stream. If you are interested, you can find it at