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Found 341 results

  1. Vonmuller

    Working with Pmod DA4

    Good morning, I'm trying to program Pmod DA4, connected to Nexys 4 DDR, using VHDL. As refernce voltage I'm using the internal reference and the maximum output should be 5V, according to the AD5628 datasheet. However, my maximum output voltage doesn't exceed 2.5V. I wonder if I'm doing anything wrong or there is actually a AD5628-1 modification is used in Pmod DA4, that allows only 2.5V as the maximum output? How can I figure out what modification of AD5628 is used in Pmod DA4? Thank you in advance. Best regards, Alex dig2an.vhd
  2. Hi: I would like to implement an application in my fpga to communicate to the PC. I don't want to use the SDK, I prefer VHDL. So, I can generate a Xilinx LogiCORE Tri-Mode Ethernet MAC using Xilinx's Coregen, but I don't know how to connect it. For example, the global clock is 125Mhz, and the atlys only provides me a 100Mhz. Should I use a clock generator? Thanks.
  3. I've been beavering away on a large project, but ended up thinking about how small a Serial TX module could be. While out splitting firewood stumbled over the idea that takes it down top 12 LUTs and 11 flip-flops library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity tiny_rs232_tx is Port ( clk : in STD_LOGIC; bit_tick : in STD_LOGIC; data : in STD_LOGIC_VECTOR(7 downto 0); data_enable : in STD_LOGIC; tx : out STD_LOGIC := '1'; busy : out STD_LOGIC ); end tiny_rs232_tx; architecture Behavioral of tiny_rs232_tx is signal shift_reg : std_logic_vector(9 downto 0) := (others => '1'); signal i_busy : std_logic; begin busy <= i_busy; with shift_reg select i_busy <= '0' when "0000000000", '1' when others; clk_proc: process(clk) begin if rising_edge(clk) then if i_busy = '0' and data_enable = '1' then shift_reg <= '1' & data & '0'; end if; if bit_tick = '1' then if i_busy = '1' then tx <= shift_reg(0); shift_reg <= '0' & shift_reg(9 downto 1); end if; end if; end if; end process; end Behavioral;
  4. Dear sir, I am working on Genesys2 board. I want pin locations of all peripherals such as I/O switches, LEDs, VGA connector, etc. Please give me .ucf file for all the peripherals available on the Genesys2 board. Thank you.
  5. k_hades1

    Pmod compability

    I've a DE0 Nano board and I wonder if Digilent Pmod modules are compatible with my board. Thanks
  6. Hi JColvin, We used zybo for our board prototype integrated with OV7670 Camera. every time I run it. I have a warning like this: INFO: [Labtools 27-1434] Device xc7z010 (JTAG device index = 1) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. Hopefully you help me to fix it! Thanks and have a nice day!
  7. aaleman

    Rpi Camera - FPGA

    HiI have been working with the Raspberry Pi Camera to make an interface with an FPGA and take the data from the camera to the FPGA memory. I want to connect the Camera Module directly with the FPGA but I have not found any document that explain the communication protocol or some procedure to make it possible to connect and configure the camera with the FPGA. If someone know any document or have an idea that can be helpful for my project I will be very grateful. Thanks.
  8. Hello, I am considering to buy a FPGA board from Digilent. I need to interface it with a chip, designed by me, which has some analog mixed signal circuitry and can have maximum voltage of 900mV. First, I am not sure as what is the output voltage level from the fpga board. If I understand correctly, it should be 3.3V in Nexys4 DDR Artix-7. Secondly, how should I regulate the output voltage from the fpga board and make it 900mV to be compatible with my chip ? In this regard, do we something in-built in the board itself ? Hoping for a prompt response from your side. Thanks and regards, Saurabh ([email protected])
  9. Kindly I need to know the difference between host and peripheral in the Pmod interfaces. Thanks
  10. RS1

    Basys 3 not mapping corectly

    I have been working on a project with my Basys 3 board and recently ran into an issue where a 16 bit signal I mapped to the LED's was displaying on my seven segment display. The signal was generated by a sudo random number gen thats I created ( the signal changes with the event of the clock). My project also includes a segment decoder which does the appropriate time multiplexing to map a different signal to the segment display. Nowhere in my code can I find the reason for this incorrect mapping, so I wrote a dummy program that did nothing but take the random number and send the signal to the LED's ( I tried indexing the signal (ie. LED(0), LED(1) etc.) as well as creating a different signal for each LED) and still the signal was not showing up on the LED's but rather made the segment display show red faintly. When I send a constant signal to the LED's they light up correctly and the display remains off, why is this? and is there anything I can do to fix this issue and make this work. I need the seven segment display for another part of my project. RandGen_txt.txt TOP_txt.txt
  11. Hi- I'm currently designing an interface board to the VHDCI connectors provided on the Genesys dev board (SKU 410-138). The schematic design doc is avalable on the resource link to the Genesys board, however not the PCB design doc. Where can I get a copy (i.e. PDF format) of the Altium PCB gerber files for this dev board? It will help me by providing guidance to design a reliable PCB with proper signal integrity by following similar layout/routing strategies. Additionally, the Genesys datasheet should have included application notes with PCB recommendations. Cheers, Emanuel
  12. Following on from playing with Arty's 10/100 Ethernet Interface, I've got a Gigabit PHY working over the RGMII interface. It is really rough, as it doesn't yet handle the slower speeds correctly, but it is able to send 979 Mb/s to my laptop (not that my Laptop can keep up with it! http://hamsterworks.co.nz/mediawiki/index.php/GigabitTX Hopefully it will be of help to somebody who wants to get a lot of data off of their FPGA board without having the overhead of a CPU and full TCP/IP stack.
  13. I have implemented the DDR3 on the Nexys VIDEO as shown in this tutorial https://reference.digilentinc.com/nexys-video/gsmb so my question is how can i mofidfied the IP MIG for reach 800 Mb/s on the nexys video? when i open the IP for modified teh parameters in clock period i set 2500 ps, input clock period 1250 ps (800 MHz), system clock : No buffer, Reference clock: Diferencial, clk_reference with pin number R4/T4, so when i run the synthesis occurs a problem in the clk_ref Note: some of the setting of my IP MIG In this part i connect the pins R4 and T4 in the CLK_ref_p and CLK_REF_n. but in the synthesis occurs a problem
  14. How to send data from pc to nexys4 through ethernet, kindly guide me how to configure the ethernet protocol in nexys4. Urgent help required.
  15. Hello, How to generate a variable duty cycle from this code? This code is for 10% duty cycle, 500 Hz frequency, but I want to generate 10%, 30%, 50%, 70% and 90% duty cycle. The clock frequency is 50 MHz. I want to generate a variable duty cycle from 5 variable frequency which are 500 Hz, 1 kHz, 50 kHz, 500 kHz, and 1 MHz. Please someone help me. I need your help. Thank you. DutyCycle(500Hz-10%).vhd DutyCycle500Hz_tb.vhd
  16. andres

    ERROR INSTALL RUNTIME

    good morning I have ubuntu operating system in version 14.4, I can not install the synthesis tool Digilent Adept runtime, I get the following error with version 14.4 and 14.6 of Digilent Adept. /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// [email protected]:/home/andres/Documentos/digilent.adept.runtime_2.16.1-x86_64# sudo ./install.sh Adept Runtime Installer 64-bit operating system detected In which directory should libraries be installed? [/usr/local/lib64/digilent/adept] Installing runtime libraries..... Checking to see if libdabs.so is already installed.... No existing installation of libdabs.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdabs.so.2.16.1" Created symbolic link "/usr/local/lib64/digilent/adept/libdabs.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdabs.so.2" Checking to see if libdaci.so is already installed.... No existing installation of libdaci.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdaci.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdaci.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdaci.so.2" Checking to see if libdaio.so is already installed.... No existing installation of libdaio.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdaio.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdaio.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdaio.so.2" Checking to see if libdemc.so is already installed.... No existing installation of libdemc.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdemc.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdemc.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdemc.so.2" Checking to see if libdepp.so is already installed.... No existing installation of libdepp.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdepp.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdepp.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdepp.so.2" Checking to see if libdftd2xx.so is already installed.... No existing installation of libdftd2xx.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdftd2xx.so.1.2.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdftd2xx.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdftd2xx.so.1" Checking to see if libdgio.so is already installed.... No existing installation of libdgio.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdgio.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdgio.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdgio.so.2" Checking to see if libdjtg.so is already installed.... No existing installation of libdjtg.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdjtg.so.2.12.3" Created symbolic link "/usr/local/lib64/digilent/adept/libdjtg.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdjtg.so.2" Checking to see if libdmgr.so is already installed.... No existing installation of libdmgr.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdmgr.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgr.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgr.so.2" Checking to see if libdmgt.so is already installed.... No existing installation of libdmgt.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdmgt.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgt.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgt.so.2" Checking to see if libdpcomm.so is already installed.... No existing installation of libdpcomm.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpcomm.so.2.15.4" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcomm.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcomm.so.2" Checking to see if libdpcutil.so is already installed.... No existing installation of libdpcutil.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpcutil.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcutil.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcutil.so.2" Checking to see if libdpio.so is already installed.... No existing installation of libdpio.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpio.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdpio.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpio.so.2" Checking to see if libdpti.so is already installed.... No existing installation of libdpti.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpti.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdpti.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpti.so.2" Checking to see if libdspi.so is already installed.... No existing installation of libdspi.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdspi.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdspi.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdspi.so.2" Checking to see if libdstm.so is already installed.... No existing installation of libdstm.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdstm.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdstm.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdstm.so.2" Checking to see if libdtwi.so is already installed.... No existing installation of libdtwi.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdtwi.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdtwi.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdtwi.so.2" Checking to see if libjtsc.so is already installed.... No existing installation of libjtsc.so found. Installed shared library "/usr/local/lib64/digilent/adept/libjtsc.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libjtsc.so" Created symbolic link "/usr/local/lib64/digilent/adept/libjtsc.so.2" Successfully installed runtime libraries. In which directory should system binaries be installed? [/usr/sbin] Installing system binaries..... installed "/usr/sbin/dftdrvdtch" Successfully installed system binaries in "/usr/sbin". Installing firmware images..... Successfully installed firmware images in "/usr/share/digilent/adept/data/firmware". Installing JTSC device list..... Successfully installed JTSC device list "/usr/share/digilent/adept/data/jtscdvclist.txt". Installing CoolRunner support files..... Successfully installed CoolRunner support files in "/usr/share/digilent/adept/data/xpla3". Installing CoolRunner 2 support files..... Successfully installed CoolRunner 2 support files in "/usr/share/digilent/adept/data/xbr". In which directory should the Adept Runtime Configuration file be installed? [/etc] Installing Adept Runtime configuration..... Successfully installed Adept Runtime configuration "/etc/digilent-adept.conf". Installing hotplug script..... cp: no se puede crear el fichero regular Ā«/etc/hotplug/usb/digilentusbĀ»: No existe el archivo o el directorio error: failed to install hotplug script "/etc/hotplug/usb/digilentusb" [email protected]:/home/andres/Documentos/digilent.adept.runtime_2.16.1-x86_64# /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// help! as I solve this problem. Thank you submit
  17. Tomar

    ARTY question

    Hi, I was wondering if it is right place to ask questions about Arty board. Thanks Tomar
  18. Takeways: 1. Maximize the usage of the Xilinx Zynq 7000 resources 2. Understand the nuances and internal workings of the Xilinx Zynq 7000 3. Trade-off performance vs. energy consumption Complexity of systems implemented using FPGA's are exponentially growing in a rapid pace. As a result of it most of the common design issues that a designer come across with ASIC SoC are becoming relevant with FPGA as well. If we consider Xilinx Zynq 7000 Programmable SoC, there is considerable processing power on the compute side. A simple migration is insufficient to achieve the same performance as discrete chips and also achieving performance and implementation benefits of such a complex FPGA would be very less. Estimating or identification of system performance and crucial bottlenecks much before writing RTL not just reduces the development time but also increases the Quality of Results. During this event we will be talking about how performance analysis and architecture exploration of a Zynq 7000 based System in the early stage of system development ensures that the right FPGA platform is selected and achieves optimal partitioning of the application onto the fabric. To Register, Click here
  19. Ryan

    Safe handling of CMOD S6?

    I am a Project Lead the Way teacher using the CMOD S6 chips during labs for most of 2nd semester. Our curriculum is designed to use these chips as a bundle with the NI MyDAQ system. I have been doing electronics for a while and understand how touchy CMOS logic can be, but I am burning through these chips weekly. I'm not sure what I'm missing here or if I received a bad batch of chips, but I have students avoiding touching the chips completely at this point, as well as having static wrist straps on. They do no wiring while the chip is powered on, and have them grounded to the board when we are using the onboard logic (buttons / switches) from the MyDAQ. Any help?? I understand I don't have much to go on here, but anyone else that has been down this road with PLTW, I'd be happy to have some advice here before I have to go spend another $1000 on chips.
  20. Min_ah

    VHDL - 10% duty cycle

    Hello, I'm new to VHDL. I need to generate 500Hz from 50MHz clock frequency. I already got it. My problem here is how should the code to be adjusted if I want to change the duty cycle to 10%? Thank you. FreqDivider500Hz.vhd
  21. Dev

    Accessing of PMODs in ZYBO

    Hello, Iam new working with ZYBO. I would like to how to access the PMODs in the ZYBO. For example connecting a LED in one of the PMOD and blinking it. Iam using Vivado 15.2 Version. Thanks in advance, With Regards, Dev
  22. Jaiko007

    3 bit output

    Hello, I need to design 3 bit output, which are 000, 001, 010, 011, 100 using FPGA. I'm using VHDL language. I have already designed it. But, the problem is I can't get that desired output I want. I got 000, 001, 011 and 111 outputs. Here I attach my code and testbench and also Isim simulator waveform part. Thank you. selectsig.vhd selectsig_tb.vhd simulator.wcfg
  23. Jaiko007

    8x1 multiplexer

    Hello, I want to design 8x1 multiplexer using FPGA. But, I just only have 5 options of input, which are freq1, freq2, freq3, freq4, and freq5. Is it possible to design it with only just have 5 options of input? If possible, how doing it? I'm using Xilinx and the language I used is VHDL. Here I attach a picture. Please help me. Thank you.
  24. Jaiko007

    MUX 2x1 using VHDL

    Hello, I need to design PWM for a multiplexer 2x1 for my project. The description is: If select = 0, output = input 1 (10kHz) If select = 1, output = input 2 (100kHz) The problem is, I don't know how to implement that frequency in my coding. Is it possible to do that. If yes, how making it? Someone please help me. Here, I attach my code. mux2to1.vhd mux2to1_tb.vhd Thank you.
  25. Hello, I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? This is for the code,FreqDivider.vhd and this is for testbench, FreqDivider_tb.vhd. Thanks.