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Found 306 results

  1. Hi- I'm currently designing an interface board to the VHDCI connectors provided on the Genesys dev board (SKU 410-138). The schematic design doc is avalable on the resource link to the Genesys board, however not the PCB design doc. Where can I get a copy (i.e. PDF format) of the Altium PCB gerber files for this dev board? It will help me by providing guidance to design a reliable PCB with proper signal integrity by following similar layout/routing strategies. Additionally, the Genesys datasheet should have included application notes with PCB recommendations. Cheers, Emanuel
  2. Following on from playing with Arty's 10/100 Ethernet Interface, I've got a Gigabit PHY working over the RGMII interface. It is really rough, as it doesn't yet handle the slower speeds correctly, but it is able to send 979 Mb/s to my laptop (not that my Laptop can keep up with it! http://hamsterworks.co.nz/mediawiki/index.php/GigabitTX Hopefully it will be of help to somebody who wants to get a lot of data off of their FPGA board without having the overhead of a CPU and full TCP/IP stack.
  3. I have implemented the DDR3 on the Nexys VIDEO as shown in this tutorial https://reference.digilentinc.com/nexys-video/gsmb so my question is how can i mofidfied the IP MIG for reach 800 Mb/s on the nexys video? when i open the IP for modified teh parameters in clock period i set 2500 ps, input clock period 1250 ps (800 MHz), system clock : No buffer, Reference clock: Diferencial, clk_reference with pin number R4/T4, so when i run the synthesis occurs a problem in the clk_ref Note: some of the setting of my IP MIG In this part i connect the pins R4 and T4 in the CLK_ref_p and CLK_REF_n. but in the synthesis occurs a problem
  4. How to send data from pc to nexys4 through ethernet, kindly guide me how to configure the ethernet protocol in nexys4. Urgent help required.
  5. Hello, How to generate a variable duty cycle from this code? This code is for 10% duty cycle, 500 Hz frequency, but I want to generate 10%, 30%, 50%, 70% and 90% duty cycle. The clock frequency is 50 MHz. I want to generate a variable duty cycle from 5 variable frequency which are 500 Hz, 1 kHz, 50 kHz, 500 kHz, and 1 MHz. Please someone help me. I need your help. Thank you. DutyCycle(500Hz-10%).vhd DutyCycle500Hz_tb.vhd
  6. andres

    ERROR INSTALL RUNTIME

    good morning I have ubuntu operating system in version 14.4, I can not install the synthesis tool Digilent Adept runtime, I get the following error with version 14.4 and 14.6 of Digilent Adept. /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// root@andres-Inspiron-N5110:/home/andres/Documentos/digilent.adept.runtime_2.16.1-x86_64# sudo ./install.sh Adept Runtime Installer 64-bit operating system detected In which directory should libraries be installed? [/usr/local/lib64/digilent/adept] Installing runtime libraries..... Checking to see if libdabs.so is already installed.... No existing installation of libdabs.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdabs.so.2.16.1" Created symbolic link "/usr/local/lib64/digilent/adept/libdabs.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdabs.so.2" Checking to see if libdaci.so is already installed.... No existing installation of libdaci.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdaci.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdaci.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdaci.so.2" Checking to see if libdaio.so is already installed.... No existing installation of libdaio.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdaio.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdaio.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdaio.so.2" Checking to see if libdemc.so is already installed.... No existing installation of libdemc.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdemc.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdemc.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdemc.so.2" Checking to see if libdepp.so is already installed.... No existing installation of libdepp.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdepp.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdepp.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdepp.so.2" Checking to see if libdftd2xx.so is already installed.... No existing installation of libdftd2xx.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdftd2xx.so.1.2.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdftd2xx.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdftd2xx.so.1" Checking to see if libdgio.so is already installed.... No existing installation of libdgio.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdgio.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdgio.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdgio.so.2" Checking to see if libdjtg.so is already installed.... No existing installation of libdjtg.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdjtg.so.2.12.3" Created symbolic link "/usr/local/lib64/digilent/adept/libdjtg.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdjtg.so.2" Checking to see if libdmgr.so is already installed.... No existing installation of libdmgr.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdmgr.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgr.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgr.so.2" Checking to see if libdmgt.so is already installed.... No existing installation of libdmgt.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdmgt.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgt.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdmgt.so.2" Checking to see if libdpcomm.so is already installed.... No existing installation of libdpcomm.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpcomm.so.2.15.4" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcomm.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcomm.so.2" Checking to see if libdpcutil.so is already installed.... No existing installation of libdpcutil.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpcutil.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcutil.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpcutil.so.2" Checking to see if libdpio.so is already installed.... No existing installation of libdpio.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpio.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdpio.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpio.so.2" Checking to see if libdpti.so is already installed.... No existing installation of libdpti.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdpti.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdpti.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdpti.so.2" Checking to see if libdspi.so is already installed.... No existing installation of libdspi.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdspi.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdspi.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdspi.so.2" Checking to see if libdstm.so is already installed.... No existing installation of libdstm.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdstm.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdstm.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdstm.so.2" Checking to see if libdtwi.so is already installed.... No existing installation of libdtwi.so found. Installed shared library "/usr/local/lib64/digilent/adept/libdtwi.so.2.8.2" Created symbolic link "/usr/local/lib64/digilent/adept/libdtwi.so" Created symbolic link "/usr/local/lib64/digilent/adept/libdtwi.so.2" Checking to see if libjtsc.so is already installed.... No existing installation of libjtsc.so found. Installed shared library "/usr/local/lib64/digilent/adept/libjtsc.so.2.9.2" Created symbolic link "/usr/local/lib64/digilent/adept/libjtsc.so" Created symbolic link "/usr/local/lib64/digilent/adept/libjtsc.so.2" Successfully installed runtime libraries. In which directory should system binaries be installed? [/usr/sbin] Installing system binaries..... installed "/usr/sbin/dftdrvdtch" Successfully installed system binaries in "/usr/sbin". Installing firmware images..... Successfully installed firmware images in "/usr/share/digilent/adept/data/firmware". Installing JTSC device list..... Successfully installed JTSC device list "/usr/share/digilent/adept/data/jtscdvclist.txt". Installing CoolRunner support files..... Successfully installed CoolRunner support files in "/usr/share/digilent/adept/data/xpla3". Installing CoolRunner 2 support files..... Successfully installed CoolRunner 2 support files in "/usr/share/digilent/adept/data/xbr". In which directory should the Adept Runtime Configuration file be installed? [/etc] Installing Adept Runtime configuration..... Successfully installed Adept Runtime configuration "/etc/digilent-adept.conf". Installing hotplug script..... cp: no se puede crear el fichero regular Ā«/etc/hotplug/usb/digilentusbĀ»: No existe el archivo o el directorio error: failed to install hotplug script "/etc/hotplug/usb/digilentusb" root@andres-Inspiron-N5110:/home/andres/Documentos/digilent.adept.runtime_2.16.1-x86_64# /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// help! as I solve this problem. Thank you submit
  7. Tomar

    ARTY question

    Hi, I was wondering if it is right place to ask questions about Arty board. Thanks Tomar
  8. Takeways: 1. Maximize the usage of the Xilinx Zynq 7000 resources 2. Understand the nuances and internal workings of the Xilinx Zynq 7000 3. Trade-off performance vs. energy consumption Complexity of systems implemented using FPGA's are exponentially growing in a rapid pace. As a result of it most of the common design issues that a designer come across with ASIC SoC are becoming relevant with FPGA as well. If we consider Xilinx Zynq 7000 Programmable SoC, there is considerable processing power on the compute side. A simple migration is insufficient to achieve the same performance as discrete chips and also achieving performance and implementation benefits of such a complex FPGA would be very less. Estimating or identification of system performance and crucial bottlenecks much before writing RTL not just reduces the development time but also increases the Quality of Results. During this event we will be talking about how performance analysis and architecture exploration of a Zynq 7000 based System in the early stage of system development ensures that the right FPGA platform is selected and achieves optimal partitioning of the application onto the fabric. To Register, Click here
  9. Ryan

    Safe handling of CMOD S6?

    I am a Project Lead the Way teacher using the CMOD S6 chips during labs for most of 2nd semester. Our curriculum is designed to use these chips as a bundle with the NI MyDAQ system. I have been doing electronics for a while and understand how touchy CMOS logic can be, but I am burning through these chips weekly. I'm not sure what I'm missing here or if I received a bad batch of chips, but I have students avoiding touching the chips completely at this point, as well as having static wrist straps on. They do no wiring while the chip is powered on, and have them grounded to the board when we are using the onboard logic (buttons / switches) from the MyDAQ. Any help?? I understand I don't have much to go on here, but anyone else that has been down this road with PLTW, I'd be happy to have some advice here before I have to go spend another $1000 on chips.
  10. Min_ah

    VHDL - 10% duty cycle

    Hello, I'm new to VHDL. I need to generate 500Hz from 50MHz clock frequency. I already got it. My problem here is how should the code to be adjusted if I want to change the duty cycle to 10%? Thank you. FreqDivider500Hz.vhd
  11. Dev

    Accessing of PMODs in ZYBO

    Hello, Iam new working with ZYBO. I would like to how to access the PMODs in the ZYBO. For example connecting a LED in one of the PMOD and blinking it. Iam using Vivado 15.2 Version. Thanks in advance, With Regards, Dev
  12. Jaiko007

    3 bit output

    Hello, I need to design 3 bit output, which are 000, 001, 010, 011, 100 using FPGA. I'm using VHDL language. I have already designed it. But, the problem is I can't get that desired output I want. I got 000, 001, 011 and 111 outputs. Here I attach my code and testbench and also Isim simulator waveform part. Thank you. selectsig.vhd selectsig_tb.vhd simulator.wcfg
  13. Jaiko007

    8x1 multiplexer

    Hello, I want to design 8x1 multiplexer using FPGA. But, I just only have 5 options of input, which are freq1, freq2, freq3, freq4, and freq5. Is it possible to design it with only just have 5 options of input? If possible, how doing it? I'm using Xilinx and the language I used is VHDL. Here I attach a picture. Please help me. Thank you.
  14. Jaiko007

    MUX 2x1 using VHDL

    Hello, I need to design PWM for a multiplexer 2x1 for my project. The description is: If select = 0, output = input 1 (10kHz) If select = 1, output = input 2 (100kHz) The problem is, I don't know how to implement that frequency in my coding. Is it possible to do that. If yes, how making it? Someone please help me. Here, I attach my code. mux2to1.vhd mux2to1_tb.vhd Thank you.
  15. Hello, I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? This is for the code,FreqDivider.vhd and this is for testbench, FreqDivider_tb.vhd. Thanks.
  16. aramosam

    Reprogram (reset) FPGA

    Hello all, I have a Nexys4 DDR and I want to reprogram it, as it's done with "PROG" button. As example I want to connect the IPROG/Program_B signal to be triggered when something happens like the output of my circuit is "1", or using a switch. How can I do that? I've read documentation about multiboot but I don't want to load two bitstreams, only one and reprogram the FPGA with it when I want. I suppose that using the Program_b signal is the way to go but I don't know how I can use it. Some code, tutorial or documentation would be appreciated. Thank you
  17. Hello, I'm using the Atlys Spartan-6 board. I want to use the LED bar in I/O ex to display the the values of 3 different counters for displaying the time of a binary clock. I try to use the information of adept advanced programming guide and some informations I gathered from But still I can't get any reaction on adept i/o ex. How can I map the outputs of out_sec<7:0>, out_min<7:0> and out_hrs<7:0> to registers 0x02, 0x03 and 0x04? Any hints for me? Sincerly, Heinz
  18. FPGAist

    Nexys4 Altium sources

    Hi, I would like to get the Altium schematics sources for the Nexys4 Artix7 board. Thanks!
  19. Hi I have done an intro to vivado simulation in Verilog based on the assignment I have done in ISE http://m.instructables.com/id/How-to-Use-Vivado-Simluation/?ALLSTEPS
  20. wheezs

    cmod 6 clock

    hey i cant finger out how to get the internal clock to use in projects
  21. C.Pallavi

    JTAG HS2

    Can we connect"JTAG HS2" cable to any VIrtex devices (Especially Virtex 2 and Virtex 4 FPGA).
  22. Evening, all. The code attempts to create a clock and synchronize it to sysclk. However, it fails timing analysis. `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Engineer: hamster, JUIXXXE ////////////////////////////////////////////////////////////////////////////////// module clk_div( input clk, output wire mclk, output wire bclk, output wire lrclk ); wire clkfb; reg [7:0] mclk_count = 0; MMCME2_BASE #( .BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW) .CLKFBOUT_MULT_F(7.0), // Multiply value for all CLKOUT (2.000-64.000). .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000). .CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). // CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128) .CLKOUT0_DIVIDE_F(57.0), // Divide amount for CLKOUT0 (1.000-128.000). .CLKOUT1_DIVIDE(14), .CLKOUT2_DIVIDE(14), .CLKOUT3_DIVIDE(14), .CLKOUT4_DIVIDE(14), .CLKOUT5_DIVIDE(14), .CLKOUT6_DIVIDE(14), // CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99). .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT3_DUTY_CYCLE(0.5), .CLKOUT4_DUTY_CYCLE(0.5), .CLKOUT5_DUTY_CYCLE(0.5), .CLKOUT6_DUTY_CYCLE(0.5), // CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000). .CLKOUT0_PHASE(0.0), .CLKOUT1_PHASE(0.0), .CLKOUT2_PHASE(0.0), .CLKOUT3_PHASE(0.0), .CLKOUT4_PHASE(0.0), .CLKOUT5_PHASE(0.0), .CLKOUT6_PHASE(0.0), .CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE) .DIVCLK_DIVIDE(1), // Master division value (1-106) .REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999). .STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked (FALSE, TRUE) ) MMCME2_BASE_inst ( // Clock Outputs: 1-bit (each) output: User configurable clock outputs .CLKOUT0(mclk), // 1-bit output: CLKOUT0 .CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0 .CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1 .CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1 .CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2 .CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2 .CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3 .CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3 .CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4 .CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5 .CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6 // Feedback Clocks: 1-bit (each) output: Clock feedback ports .CLKFBOUT(clkfb), // 1-bit output: Feedback clock .CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT // Status Ports: 1-bit (each) output: MMCM status ports .LOCKED(LOCKED), // 1-bit output: LOCK // Clock Inputs: 1-bit (each) input: Clock input .CLKIN1(clk), // 1-bit input: Clock // Control Ports: 1-bit (each) input: MMCM control ports .PWRDWN(1'b0), // 1-bit input: Power-down .RST(1'b0), // 1-bit input: Reset // Feedback Clocks: 1-bit (each) input: Clock feedback ports .CLKFBIN(clkfb) // 1-bit input: Feedback clock ); assign bclk = mclk_count[2]; // mclk / 8 assign lrclk = mclk_count[7]; // mclk / 256 reg mclk_last; always@(posedge(clk)) begin if(mclk & !mclk_last) mclk_count <= mclk_count + 1; mclk_last <= mclk; end endmodule From CLKOUT0 to mclk_count fails timing analysis. How can the code be restructured to avoid this?
  23. Greetings everybody, I recently purchased a Zybo (Zynq 7000 series application board), currently I am experimenting around with it a bit. This is the first time I am working with FPGAs, up to now I have only been working with other microcontrollers and cortex processors. While looking for reading material, I stumbled across this example, which shows how to create and use custom IP cores using Vivado. Since it is an official example from digilent and other examples worked without problems I though this one would be easy to follow, too. Problem is, it doesn't work. I am following each and every step exactly as shown in the pictures and described in the text. After successfully generating the bitstream (no warnings/errors) and exporting it I run the SDK. The C code there compiles, too, I program the FPGA and launch the compiled ELF using GDB on the Zynq. Here I first have to turn off the "Run ps7_init" and "Run ps7_post_config" checkboxes in the run configuration, otherwise the elf won't run on the Zynq. Now the ELF runs on the Zynq (or at least I hope so...), but nothing happens. Nothing at all. The LEDs are supposed to start pulsing, but they don't. Does anybody have similar experience with the given example? Or can anyone tell me what's wrong or how to find out? I'm greatful for any help you might have to offer. I currently am using Vivado 2015.4 (64 bit). Best regards, Daniel
  24. Hi all, I've recently bought an Arty board (Microblaze processor) and some Pmods (PmodDPOT, PmodDAs, PmodADs), which use SPI protocol. I've looked everywhere for an example on how to access the Pmod headers or just how to use Pmods with the Arty but I couldn't find anything (even on the reference wiki page for the Arty). I found a library for SPI on Xilinx SDK which is called Xspi but I also am not sure how to use it. Can anybody perhaps help me by giving me the basic steps on how to do this? I'm very new to FPGA, so any feedback or suggestions are welcome! Thanks Viv
  25. When I updated the FTDI VCP drivers(http://www.ftdichip.com/Drivers/VCP.htm ,win7 X64 2.12.10), the ARTY onboard JTAG disappeared. And there are two USB-TO-COM on my computer. See attachment, please. Any suggestions? JTAG.not.work.rar