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Found 311 results

  1. Hello, I want to access analogue pin of XADC header to input audio data in FPGA (Virtex VC707 here). But i am getting error in writing bit-stream "Partially routed nets". Design is below: As we provide the pin number and voltage standard in constraint file for pin assignment, but here the I/O Std is faded and cannot be edited. I have also edited constraint file manually but still getting this error. Pin assignment are as under for VC707 Schematics diagram for VC707 Any help will be appreciated. Thanks,
  2. I'm still relatively new to Verilog and FPGA programming, so I've been struggling quite a bit with this one. The goal of the project here is to play a super basic game of 'blackjack' and I can't quite seem to get the system to work. As a note: The game goal is to get to 21, but a number reasonably high and close to 21 could still win the game based on what the Dealer has. The first few if - else if statements are there to interpret the card input from switches on the basys3, and then decide how much to add to the count based on the 'card' input. The latter if - else statement is there to output either an 'H' or an 'S' to the 7-segment display in order to output whether the player should 'hit' and recieve another card, or if that person should 'stay' and just hold onto the cards they have. For some reason, the board only displays the 'H' value on the 7 segment display, and I have no way to find out if the count is actually incrementing in the program since I can't figure out how to test this outside of the board. Any assistance would be greatly appreciated. As a note: I have checked the constraints file, and everything looks correct. blackjack.v verilog file: module BlackJack(input clk, ace, four, five, six, eight, jack, reset, output clk_slow, reg A, B, C, D, E, F, G, H, wire segEn, segEnd); //slow clock code parameter clkbit = 27; reg [clkbit:0] clk2 = 0; always@(posedge clk) begin clk2 <= clk2+1; end assign clk_slow = clk2[clkbit]; reg count = 0; assign segEn = 0; // enable for the 7-segment display assign segEnd = 1; always @(posedge clk_slow) begin if (count <= 10) //states from start to 10 - card decisions made here begin if (ace) count <= count + 11; //adds 11 else if (four) count <= count + 4; else if (five) count <= count + 5; else if (six) count <= count + 6; else if (eight) count <= count + 8; else if (jack) count <= count + 10; else count <= count; end else if (count <= 11) // states from 11 to 17 begin if (ace) count <= count + 1; //adds 1 else if (four) count <= count + 4; else if (five) count <= count + 5; else if (six) count <= count + 6; else if (eight) count <= count + 8; else if (jack) count <= count + 10; else count <= count; end else if (reset) begin count <= 0; end else begin count <= count; end if (count < 17) begin F <= 1'b0; B <= 1'b0; G <= 1'b0; E <= 1'b0; C <= 1'b0; A <= 1'b1; D <= 1'b1; end else begin A <= 1'b0; F <= 1'b0; G <= 1'b0; C <= 1'b0; D <= 1'b0; B <= 1'b1; E <= 1'b1; end end
  3. Hello, I am new to Xilinx and I am trying to execute the Embedded Vision Demo on Vivado 2017.4 version (attached below). This is my first time working with Block Designs and HLS so can you please guide me on how to successfully perform the mentioned demo project. Following the Read_me file I have generated the block design of the demo on Vivado. However, I am unable to export the project to SDK as it gives the error "Cannot write hardware definition file as there are no generated IPI blocks" (I am not sure if this is correct next step but I am trying follow the reference manual of z7-20 pcam 5c for this demo as well). Kindly guide me with the steps to be followed in order to get the demo working. Reference manual : https://github.com/Digilent/Zybo-Z7-20-pcam-5c?_ga=2.170407588.585429254.1575373921-868278974.1575373921 Thanks. EmbeddedVisionDemo.pdf
  4. Hello, We are working on an older system with a Virtex-II pro with rocket I/o and would like to know if the NetFPGA Virtex-II Pro FPGA Development System would be a suitable development board ( it is the same fpga I just need to see if it supports rocket I/o).
  5. Hi, I'm trying to use Pmod WiFi on a Zynq board for a school project and it is required to add WiFi feature to the boards so that the mother board can send to the other boards. I built the basic block diagram but I'm not sure whether it works because when I run the template projects from Digilent/vivado-library on github, there is no response at the terminal, nothing happens. Does the board need a SD card for setting up a TCP/UDP echo server/client (there is already a SD card slot on my zynq board)? Also, can someone take a look at my block diagram to make sure it is correct? Thanks, everyone.
  6. Hello, What would be the system requirements for an FPGA based board that has the capability to connect to the cloud (IoT features). Its application will be the object detection and tracking. Therefore, we will be needing a camera connected to the board. Could you, please, give any suggestions regarding the whole system requirements (other than the board)? Thanks in Advance,
  7. Hello to everybody! I'm built custom Embedded Linux distro which based on Digilent Base-Linux FPGA design (https://github.com/Digilent/Zybo-Z7-20-base-linux) with help Xilinx Petalinux env. In this design was implemented XADC support. From the default BSP package from Digilent repository, I added support XADC to the device tree. How I can test this implementation from a working Linux image. I need to write a driver or I already can work with XADC?
  8. Hi everyone ! I'm working on the zybo board. There is a yocto linux on a SD card, and the system boot on the SD card. This works very well. Now I really enjoy if I could understand how to link vivado (to generate bitstream) and yocto ! I'm a little lost about this link. I read that some people say to use the layers meta-xilinx-tools ? Someone already use it ? I don't really understand how to use it, and how manage the boot.bin, u-boot, fsbl ... etc Could you help me please ? best regards, Yohan
  9. SDK fatal error:xgpio.h no such file or directory I am using: Vivado 2016.4 Design Tools Windows10 on a Lenovo Ideapad Zybo dev. board with the Zynq7020 While following the first exercise in The Zynq Book Tutorial. I encountered several errors but they seemed harmless enough since I was able to successfully create and export a bitstream. But now I am wondering if those warning and errors from the IP Integrator stage is causing my inability to build the project LED_test_tut_C.c code in the SDK, receiving fatal error:xgpio.h:No such file or directory. When looking in "C:\Zynq_Book\first_zynq_design\first_zynq_design.sdk\LED_test_bsp\ps7_cortexa9_0\include", there is indeed no "xgpio.h" file. Could this be due to errors I received in the during implementation? Such as: WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. [C:/Zynq_Book/first_zynq_design/first_zynq_design.runs/impl_1/.Xil/Vivado22392YogaFlex/dcp_3/first_zynq_system_axi_gpio_0_0.edf:3791] I think the first of which was: "ERROR: [Ipptcl 7-1] Could not find packager TCL script '/scripts/ip/ipx.tcl'" Another was: ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_xilinx_com_ip_processing_system7_5_5': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing"source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_xilinx_com_ip_processing_system7_5_5 ]" and CRITICAL WARNING: [IP_Flow 19-973] Failed to create IP instance 'first_zynq_system_processing_system7_0_0'. Error during customization. The list continues (can provide full more tcl messages and logs) but I was able to generate a bitstream. Another aggravating factor could be that I ran into the 2012 Microsoft C/C++ Redistributable compatibility issue when starting the SDK from within the IDE. To solve that problem I renamed xvcdredlist.ext in the "C:\Xilinx\SDK\2016.4\tps\win64" folder and launched from the Start menu. Since most of the errors encountered have to do with input/output and GPIO, I kind of think and hope that the root problem has to do with the following warning thrown in the Vivado 2016.4 IDE / IP Integrator synthesis/ implementation: "WARNING: [Constraints 18-550] Could not create 'IOSTANDARD' constraint because net 'first_zynq_system_i/axi_gpio_0/gpio_io_o[0]' is not directly connected to top level port. 'IOSTANDARD' is ignored by Vivado but preserved for implementation tool. " My question is whether all these errors received in the implementation stage are related to the error in the SDK. If that is the case than would solving the following error ( the very first error) solve all? if so how would I go about that? If in your answer you could as much explanation as needed to help me understand how to troubleshoot this myself, it would be most appreciated. As I am new to FPGA development. This is the tcl command that started it all: "create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0" and produced this: couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory ERROR: [IP_Flow 19-2234] Failed to initialize IP Tcl interpreter '::ipgui_design_1_c_addsub_0_0': couldn't read file "C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl": no such file or directory while executing "source C:/Xilinx/Vivado/2016.4/scripts/ip/xit/1.0/init.tcl" invoked from within "interp eval ::ipgui_design_1_c_addsub_0_0 ]" If these warnings and errors are unrelated could I successfully download the bitstream to my Zybo board without fixing the errors encountered while using the IP Integrator and only fixing the fatal error: xgpio.h: No such file or directory in the SDK? If so, is the best way to do that? Finally just to recap my questions are to help me understand the warning/error messages and ultimately resolve the xgpio.h no such file error, and as follows in no particular order: What dose first_zynq_systemj/axi_gpio[0] is not directly connected to top level port mean? As this would help me solve the IOSTANDARD error. Would renaming xvcredlist.exe create problems elsewhere? What is this tcl command trying to achieve and why is giving the error? create_bd_cell -type ip -vlnv xilinx.com:ip:c_addsub:12.0 c_addsub_0 Why can I see xgpio.h in the project explorer tab under src/LED_test_tut1C.c but not under the C/C++ projects tab? How can I fix the xgpio.h: no such file or Directory in the SDK? Thank you for your attention. I apologize for the wordy post and welcome anyone who can shed light on any of these questions.
  10. Any & all help is appreciated with this thread. I am 100% new rookie to FPGA. I purchased the Digilent Zybo Z7: Zynq-7000 ARM/FPGA SoC Development Board (Zybo Z7-20 with SDSoC Voucher) My intentions are to crypto currency mine a new FPGA algo called Odocrypt created by the blockchain group Digibyte DGB. Here are a couple links to the info. https://www.dgbwiki.com/index.php?title=FPGA_mining https://www.coinfoundry.org/pool/dgb5 DigiByteCoin Github Odocrypt Mining Software https://github.com/DigiByte-Core/odo-miner It will change every 10 days. Its supposed to, to make it more ASIC resistant. I thought this may make a nice marketing tool also that is profitable & I'll gladly promote if someone can tell me how to set it up! Any input, insight or suggestions how to setup the Xilinx software for this particular FPGA to mine that Odocrypt algo on that mining pool... would be greatly appreciated! TYIA
  11. Hi, I have a brand new Digilent A7-35T board I tried to program via the USB built in JTAG using Vivado 2018.2. The part intermittently shows up in Hardware Manager, but a seconds later disconnects. Sometimes it disconnects just being connected (opened) in Hardware Manager and sometimes during programming. It is even worse if I try to erase and program the QSPI flash. I also downloaded and installed the latest Digilent Adept 2 with updated drivers and observed the same behavior. I tried different USB cables, different USB ports directly on my PC, via a powered hub, but the behavior is always the same -- it intermittently disconnects and fails. The amber LED does however stay lit. In Device Manager I am able to see the FTDI UART. I did also see it enumerate as a Microsoft BallPoint Mouse -- whatever that is. With this exact same setup, PC, Vivado, USB cables, etc, I have been programming the Zybo Z7-20 and the Arty boards with several designs without any such issues. Please let me know if I missed anything and what are the next steps in getting the board replaced or fixed. Thanks.
  12. Hi all, Currently I am working on a project with the aim to encrypt the communication between a drone and the ground station by using an PYNQ-Z1 board. I am facing the issue of how to convert the standalone application (bare metal) to a Linux base application in Vivado 2019.1 SDK, in order to make use of the crypto++ libray which requires the presence of an perating system to work. Does anyone know what to do to slove the issue? Thanks George
  13. I am learning how to operate an FPGA, and I have to input a signal (which in itself is the output of a discriminator), and analyze it through a Basys3 FPGA. Looking at the available ports on the board, I'm guessing that it could be done using the Pmod ports, but even after hours of googling and going through the manuals, I failed to know which data ports to use, and how to read the signal after I've input it through the board. I've got references to some boards, in which GPIO ports are explicitly labelled, but I don't see any such labeling on the Basys3. So, it'd be really helpful if someone can provide me with any insight regarding this. Any other references or links would also be greatly appreciated. I've already gone through the basic tutorials (like lighting the led using the switch. I just want to know how to use the input ports, and analyze my signal. Thank You
  14. I am working in an DSP algorithm, I have generated the bitstream for that algorithm and dumped into FPGA basys 3 board (the output of the algorithm is of 16-bit wide and consists of 100 samples). Now, I need to view the waveform with the help of Waveforms software and analog discovery kit. So, how it can be done? Can anybody provide me some video or anyother material that can solve the problem. #So far information obtained# In the material "Basys 3™ FPGA Board Reference Manual Overview" page no. 18, since, my data is of 16-bit wide I have connected pmod pins JB1 to JB4 to analog discovery pins 0 to 3 and JB7 to JB10 to analog discovery pins 4 to 7 to transfer first 8-bit. Similarly, JC1 to JC4 and JC7 to JC10 are connected to the 8 to 11 and 12 to 15 no pins of analog discovery. Is the connection is ok? What will be other connections needed?
  15. Hello everyone I am a student in bachelors and I am working on a project combining Digital Image Processing and FPGA programming. The project consists of global image thresholding but should be done real-time by the FPGA and returning the output image back to PC/laptop. I have the Nexys Video board but I still haven't figured out how to "import" the images. Is it even possible to store data in the FPGA's buffer/RAM? If someone could help me with importing/exporting data I would be very grateful. My course in FPGA includes programming in VHDL instead of Verilog, so that's the one I am using. Every information would be helpful.
  16. Hello, I am kind of new to FPGAs and I am trying to use the XADC in order to monitor the temperature sensor: I am using Vivado 2018.2, Nexys video as a board. I used the IP catalog in order to set up the XADC as following: DRP, Single channel, continuous, disable all alarms, disable reset_in, channel to monitor: temperature I wrote a top level module which reads the bits 4 up to 7 from do_out and light up LEDs accordingly: //part of the top module: module top( input CLK100MHZ, input vp_in, input vn_in, input [1:0] sw, output reg [11:0] LED ); wire enable; wire ready; wire [15:0] data; reg [6:0] Address_in; xadc_wiz_0 XLXI_7 (.daddr_in(Address_in), //addresses can be found in the artix 7 XADC user guide DRP register space .dclk_in(CLK100MHZ), .den_in(enable), .di_in(0), .dwe_in(0), .busy_out(), .vn_in(vn_in), .vp_in(vp_in), .alarm_out(), .do_out(data), .eoc_out(enable), .channel_out(), .drdy_out(ready)); always @( posedge(CLK100MHZ)) begin if(ready == 1'b1) begin case (data[7:4]) 4'b0001: LED <= 12'b000000000001; 4'b0: LED <= 12'b0; 4'b1000: LED<=12'b000000000010; default: LED <= 12'b1; endcase end end ///// I have one problem though, as I come to set the address of the ddr_in as done in a documentation found here which has LEDs displaying potential differences monitored by XADC, I do not understand what 8 bit address I should assign for the DRP to monitor the Temperature Channel ! "Address_in <= 8'h ????" My goal: I need the LEds to display something for the sake of demonstration that I am able to read values out of the do_out. Thank you for your help.
  17. birca123

    ZYBO HDMI-IN

    Hello, I have a problem with the HDMI-IN example for ZYBO. As an input, I'm using FPV camera which has an analog output, and between the camera and ZYBO is AV2HDMI converter, which upscales NTSC resolution to 1080p or 720p HDMI signal. The problem is that ZYBO says that video capture resolution is 3996x5 when the output resolution from the converter is 720p and 3996x0 when the output resolution is 1080p. When I connect the camera to the TV as HDMI source, everything works perfectly. Is this solvable? Or should I use another HDMI source for this example? Best regards, Toni Birka
  18. Dear Team, We have established Ethernet communication on Arty-7 35 T for FPGA to PC (Transmission) and PC to FPGA (Reception). We have done RTL design without using micro-blaze and On system side we are using Visual studio for sending commands to FPGA using socket programming. We are facing following problems which are given below : FPGA to PC communication works perfectly for any IP address, but When we send command from socket for PC to FPGA communication, Ethernet on FPGA only listen to xxx.xxx.1.255 - broad cast IP. FPGA does not listen to any other value than 255. What could be reason behind this? Another problem we observed related to wire shark. While having Ethernet communication, If we close wire-shark, FPGA stops sending data. We are not able figure the main cause.
  19. ozden.erdinc

    Vivado AXI QUAD SPI

    Hello, I am dealing with Vivado Ip cores. I want to design SPı interfaces by using AXI QUAD SPI in microblaze. Unfortunately, when I designed my cores and when I generated bitstream Imy designed failed. Also I added DDR3 because I tought that maybe Microblaze caches are not enough for SPI. Before the generating bitstream I get these critical warning in the validation session. When I ignore these warning as we know that my block designs failed. Can you help me this issue? I am really dealing with with it . I would really appreciate it.
  20. I want to use GNU RADIO to design an RF signal receiving circuit. For this I plan to use an FPGA card in the baseband section of the circuit (to handle the decimation and, if possible, to convert analogue to digital signal). My doubt lies in knowing if it is possible to communicate the FPGA card to the GNU RADIO application directly or if necessary from an external program. At this point it should be noted that I work in windows 10. I'm quite new on the subject of FPGA and GNU RADIO. I would really be grateful if you help me with this problem. The card is a Xilinx Zynq-7000 Developmet Board, the Z-7010, its features are best seen on the next page https://reference.digilentinc.com/reference/programmable-logic/zybo/reference-manual Suggestions for design changes are welcome. In advance thanks for the help.
  21. YakirP

    Pmod wifi SDK problem

    Hi i'm using Vivado 2018.2 + Zedboard, my goal is to use the WiFiScan from the examples attached to Pmod WiFi folder. i have build the project in vivado section and exported it to SDK at that point i'm creating new application project, choose C++ project and select finish. i'm getting the following errors: flexible array member 'DHCPDG_T::options' not at end of 'struct DHCPMEM_T' DHCP.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 216 C/C++ Problem flexible array member 'DHCPDG_T::options' not at end of 'struct DHCPMEM_T' DHCP.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 216 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class TCPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class TCPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class UDPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'class UDPSocket' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'struct DNSMEM_T' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/include/DEIPcK/utility‬ line 145 C/C++ Problem flexible array member 'SMGR_T::rgPages' not at end of 'struct DNSMEM_T' HeapMgr.h ‪/proj_bsp/ps7_cortexa9_0/libsrc/PmodWIFI_v1_0/src/DEIPcK/utility‬ line 145 C/C++ Problem thanks for the help
  22. I use a Nexys 4 DDR board for some time now. I never used to have problems when programming the device. Today I tried to program the device as I did many times before, but it didn't work. It said I should check whether I connected the board properly and so on. So I checked the Jumper settings and everything. Now I tried to see whether the FTDI FT2232HQ chip is recognized. When using the bash command "lsusb" the chip is not listed anymore. Does anyone know what the problem could be? How else could I check whether the FTDI FT2232HQ chip is working or not? I need to finish a report and therefore I need the device working as soon as possible, thank you for your help.
  23. vivado version :2018.2 Project source download from : https://github.com/Digilent/ZedBoard-FMC-Pcam-Adapter-DEMO/releases/download/v2018.2-1/ZedBoard-FMC-Pcam-Adapter-2018.2-1.zip?_ga=2.123110859.1144416419.1559024388-476519465.1556766573 In the SDK main.cc: 1.I manual add #define XPAR_MIPI_D_PHY_RX_NUM_INSTANCES 4. 2. how to define the XPAR_VIDEO_SCALER_A_DEVICE_ID ? 3.I choose random number to XPAR_VIDEO_SCALER_(A~D)_DEVICE_ID.It's show the errors, how to solve ? thank your much for your help
  24. Is it possible to write a VERILOG / VHDL code to download the programming file (fpga bitstream) to the hardware device (for example an SPI flash memory)? I'm asking this, because I would like to transfer a bit stream into a spi flash memory, which will then be mounted on an fpga card for boot and configuration. I have already written a few lines of code to write, read, and erase the contents of the 32 MB NOR flash memory (PMODSF3). I tested my code and it works without problems! However, how to read the bitstream, before writing it to the flash memory? Do I only need to transfer the bitstream into flash memory or do I have to add a header and a footer in the memory before and after the transfer of the bitstream file? Have you ever worked on a similar project? N.B: I am using a Xilinx FPGA (Artix-7) on a customized board. I would like to find an alternative solution to the Xilinx hardware manager to program the SPI flash. Any ideas, feedbacks and suggestions are welcomed! Thank you Hervé