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Posts posted by ababa

  1. Thanks for your valuable answer;

    For the complete project "hello_world", may you give me the link to its tutorial? This design works well without any problem. While the tutorial you have cited in your answer doesn't give the same final design; but it generates an error message that appears later  "MicroBlaze is under RESET. Check if the Reset input to MicroBlaze and its Bus Interfaces are connected properly UNABLE to STOP MicroBlaze". 



  2. I'm using SDK 2018.3 for the first time

    I've correctly sent the bitstream file from Vivado 2018.3 

    Then; I launched SDK 2018.3, I did the following:

    File->New->application project (then give the name of the project then select for example the code hello_world)

    Click SDK terminal; then select the choice: (connect to a serial port)

    Xilinix->Program FPGA

    Under Project Explorer; right click on the project file; then I selected :

    Debug as-> Launch on Hardware (GDB)

    I got the error illustrated on the attached screenshot; I have the impression that I missed doing something! what I have to do to avoid that error?



  3. Hi;

    I'm trying to make a Microblaze based embedded microprocessor using Nexys 4 DDR and Vivado 2018.3.

    For the same model, Vivado generates Bitstream file for another board (Artix 7 AC701 evaluation form) but for my board (NEXYS 4 DDR) Vivado doesn't generate the bitstream file. 

    May I find any logic reason ?? 

    Even though I have included the board "NEXYS 4 DDR"  in the list of board_files inside Vivado. But in any case, it doesn't work!