bhall

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Everything posted by bhall

  1. Exactly. You should be able to program the flash using the same method, just without having the convert to SREC box checked.
  2. Thanks @kwilber for this information. I was familiar with the tutorial you shared, but I hadn't tried changing compiler optimization flags, as they suggested. That decreased my file sizes, making it finish more quickly. It was still too slow for me, probably because my .srec is still pretty large. I didn't try the steps in the second link you shared, but I appreciate your assistance. (For others with a similar problem): Instead of using the SREC SPI bootloader, I used this ELF Bootloader. It worked a lot better for me, but I did have to change a couple of the definitions in eb-config.h. I changed SPI_READ_OPERATION to 0x3 and SPI_FLASH_NDUMMY_BYTES to 0 as specified by my flash memory's datasheet. I also changed ELF_IMAGE_BASEADDR to fit my storage needs. It boots my .elf in about 3 seconds, compared to the SREC bootloader which took ~2.5 minutes. Maybe I had something configured incorrectly for that one...
  3. Hello, I am using Vivado 2018.3 and a XC7A100T Artix-7. My project includes a Microblaze and an AXI QSPI controller. I am attempting to boot an SREC from Spansion Flash (S25FL256L) using the SREC SPI Bootloader. My SREC file size is around 830 KB. It takes over 2 minutes for the bootloader to finish loading the SREC. I commented out the VERBOSE definition, so nothing is being printed. Stack and heap sizes for the Bootloader are 2KB. Does anyone have an idea as to how can I reduce this time? I have tried increasing the clock frequency that is connected to my AXI QSPI controller (ext_spi_clk), but this did not help. I have also tried changing the bitstream configuration settings, but apparently that is for the initial FPGA configuration. I even tried an ELF bootloader found on Github, but it gave an error saying that my ELF header is invalid. Has anyone found a solution to this problem? I have seen several posts on these forums regarding this, but have found no clear solutions... Thanks in advance, Brad
  4. bhall

    NEXYS 4 Programming Flash

    @jpeyron and @D@n, Thank you both for your responses and advice. I think the question I have now mainly applies to the project that Jon provided. I am doing my best to make sure that my project has the same setting as yours does. I am confused about the qspi clock that is an output from the FPGA and is an input to the flash memory. It is not listed in the port map on the top level of your design, so is it inferred or constrained somewhere? In the Nexys 4 board file (and other documentation) I see that pin E9 is meant too be used for this purpose. Why is there no external port or pin visible for this in your project? I am wondering if this is the reason why my srec spi bootloader cannot receive the device data from the flash itself. Since I am using a XDC file rather than the board file, is it possible that qspi_sck is not getting configured/connected correctly? Hopefully this makes sense. Again, I really appreciate the help from both of you! Brad
  5. bhall

    NEXYS 4 Programming Flash

    Hi @jpeyron, Unfortunately I am still having problems with this. I am now trying to create a similar project for a custom board. Because of this, I need to write my own XDC file for my specific device (XC7A100T-1CSG324C) rather than using the board file. I used the XDC provided by Digilent as a template. I believe that I have not configured QSPI correctly because when I run the SREC SPI bootloader generated by SDK it does not make it past the XIsf_Initialize´╗┐() function. I used the debugging tool to investigate the problem here and it turns out that none of the device or manufactuer information is being passed to the IntelStmFlashInitialize() function. Is there any way you or someone at digilent could share a (preferably VHDL) project that uses a custom XDC rather than the board file? I think my issue and confusion stems from porting the signals in the project's top file to the external signals. I'm also getting confused by the IOBUFs that I may or may not need... If any of this needs clarification or elaboration please let me know. I appreciate your help! Thanks, Brad
  6. bhall

    NEXYS 4 Programming Flash

    Hi Jon, Thanks for sending me this. I spent most of the day trying to get this to work and this is what I have figured out... First, my problem was that my MicroBlaze did not have boxes checked for "Use Instruction and Data Caches" and "Use Cache for All Memory Accesses". I think this is what was preventing me from being able to place code sections into the external memory. I was able to select the axi_emc option after changing these settings. After this was resolved my next problem was that the srec spi bootloader would not finish and load the srec that I was storing in flash. This occured in my project and the one you provided as well. The bootloader program was getting stuck at the XIsf_Initialize() function. It turns out that our AXI Quad SPI IP cores were configured to be in QUAD mode while the bootloader program expects it to be in Standard mode. This can be changed by re-customizing the IP. You also have to verify that in the project settings the bitstream configuration Bus width (under SPI Configuration) is set to 'NONE' and the Configuration Mode is set to 'Master SPI x1'. You can then generate the bitstream, export hardware, and launch SDK. Following the rest of the "How To Store Your SDK Project in SPI Flash" was successful after that. Everything seems to be working as expected. Hopefully this helps others. Thanks again for your assistance! Let me know if you have any questions. Brad
  7. bhall

    NEXYS 4 Programming Flash

    Hi Jon, Thanks for your reply. I'll try compressing the bitstream. I did power cycle the board after configuring, and jp1 is in the qspi position. The project functions correctly when I simply configure the FPGA with the program .elf. Not sure why it won't let me use the external RAM, but I'll try to implement my project using BRAM. I'll update if I figure it out. I might try posting on Xilinx forums. Thanks again. Happy Holidays! Brad
  8. bhall

    NEXYS 4 Programming Flash

    Hello, I am attempting to store a SDK program in SPI flash on a NEXYS 4. It is being powered via USB. My block diagram and C program are almost the same as in "Getting Started with the Vivado IP Integrator". I am using MicroBlaze. I followed the tutorial "How To Store Your SDK Project in SPI Flash". The problem I am having is that unlike the tutorial, the nexys 4 does not have DDR, so on step 2.3 my only option for "Place Code Sections in:" is the MicroBlaze memory (see attached image). For "Place Data Sections in:" and "Place Heap and Stack in:" I can select the axi_emc memory that I assume communicates with the Cellular RAM on the board. I believe this is the problem but I'm not 100% sure. I can edit the lscript.ld to have all of the memory regions under axi_emc (see other attached image), but my program does not seem to be running after completing the remaining steps. I know that the issue is not not my block design or C program because I was able to successfully store and run it from flash using this tutorial. https://www.instructables.com/id/Flashing-a-MicroBlaze-Program/ The only problem with using the second method is that it runs the program in the FPGA's BRAM (I think). This might be an issue for me in the future if my program can not fit in the BRAM. Can anyone suggest a solution to my problem? Like I said, the other steps in the "How To Store Your SDK Project in SPI Flash" tutorial seem like they are finishing correctly but after programming and reboot, the "DONE" light turns on, but button presses do nothing to the lights and nothing appears in the terminal. Thanks for your time and assistance in advance. Let me know if anything needs clarification. Brad