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  1. Exactly. You should be able to program the flash using the same method, just without having the convert to SREC box checked.
  2. Thanks @kwilber for this information. I was familiar with the tutorial you shared, but I hadn't tried changing compiler optimization flags, as they suggested. That decreased my file sizes, making it finish more quickly. It was still too slow for me, probably because my .srec is still pretty large. I didn't try the steps in the second link you shared, but I appreciate your assistance. (For others with a similar problem): Instead of using the SREC SPI bootloader, I used this ELF Bootloader. It worked a lot better for me, but I did have to change a couple of the definitions in eb-confi
  3. Hello, I am using Vivado 2018.3 and a XC7A100T Artix-7. My project includes a Microblaze and an AXI QSPI controller. I am attempting to boot an SREC from Spansion Flash (S25FL256L) using the SREC SPI Bootloader. My SREC file size is around 830 KB. It takes over 2 minutes for the bootloader to finish loading the SREC. I commented out the VERBOSE definition, so nothing is being printed. Stack and heap sizes for the Bootloader are 2KB. Does anyone have an idea as to how can I reduce this time? I have tried increasing the clock frequency that is connected to my AXI QSPI controller (
  4. bhall

    NEXYS 4 Programming Flash

    @jpeyron and @[email protected], Thank you both for your responses and advice. I think the question I have now mainly applies to the project that Jon provided. I am doing my best to make sure that my project has the same setting as yours does. I am confused about the qspi clock that is an output from the FPGA and is an input to the flash memory. It is not listed in the port map on the top level of your design, so is it inferred or constrained somewhere? In the Nexys 4 board file (and other documentation) I see that pin E9 is meant too be used for this purpose. Why is there no external port or pin visi
  5. bhall

    NEXYS 4 Programming Flash

    Hi @jpeyron, Unfortunately I am still having problems with this. I am now trying to create a similar project for a custom board. Because of this, I need to write my own XDC file for my specific device (XC7A100T-1CSG324C) rather than using the board file. I used the XDC provided by Digilent as a template. I believe that I have not configured QSPI correctly because when I run the SREC SPI bootloader generated by SDK it does not make it past the XIsf_Initialize´╗┐() function. I used the debugging tool to investigate the problem here and it turns out that none of the device or manufactuer infor
  6. bhall

    NEXYS 4 Programming Flash

    Hi Jon, Thanks for sending me this. I spent most of the day trying to get this to work and this is what I have figured out... First, my problem was that my MicroBlaze did not have boxes checked for "Use Instruction and Data Caches" and "Use Cache for All Memory Accesses". I think this is what was preventing me from being able to place code sections into the external memory. I was able to select the axi_emc option after changing these settings. After this was resolved my next problem was that the srec spi bootloader would not finish and load the srec that I was storing in flash. This o
  7. bhall

    NEXYS 4 Programming Flash

    Hi Jon, Thanks for your reply. I'll try compressing the bitstream. I did power cycle the board after configuring, and jp1 is in the qspi position. The project functions correctly when I simply configure the FPGA with the program .elf. Not sure why it won't let me use the external RAM, but I'll try to implement my project using BRAM. I'll update if I figure it out. I might try posting on Xilinx forums. Thanks again. Happy Holidays! Brad
  8. Hello, I am attempting to store a SDK program in SPI flash on a NEXYS 4. It is being powered via USB. My block diagram and C program are almost the same as in "Getting Started with the Vivado IP Integrator". I am using MicroBlaze. I followed the tutorial "How To Store Your SDK Project in SPI Flash". The problem I am having is that unlike the tutorial, the nexys 4 does not have DDR, so on step 2.3 my only option for "Place Code Sections in:" is the MicroBlaze memory (see attached image). For "Place Data Sections in:" and "Place Heap and Stack in:" I can select the axi_emc memory that I as