Eddie

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  1. Glad to hear deleting the other directories in the project fixed the errors. Unfortunately, we have not had time to make an IP Core for the PmodDA4. The PmodDPG1 has the same pin out as the Pmod DA4. I would use the PmodDPG1 IP Core and alter it to work with the Pmod DA4. I would use the arduino example here and the AD5628 datasheet as a reference for how to configure and use the Pmod DA4. Hey jpeyron, Bringing up this year old project again, Just wanted a sanity check here. I did a compare of the ip for the DA1 and the DPG1 and they are identical except for names. So I'm realizing from a hardware perspective, if it's a SPI interface to the AXI bus, it doesn't matter what's on the other side of the PMOD as long as the data direction is the same (MOSI/MISO; and even in this case it doesn't matter because even though the ref manual says some pins aren't hooked up, they are in the verilog code for the PMOD bridge.) any SPI IP will work. Thanks, Eddie
  2. Ok so I finally got it working. The module is fine. I had enabled instruction and data caches in the microblaze. After turning those off and regenerating everything I can now see Tom's wonderful smile. Thanks for the help
  3. Ok thanks that's good to know. I've been able to run the main.c from the oledrgp ip demo. it seems to be running, meaning the code is running. But there is nothing coming through onto the actual PMOD. I switched it to a high speed PMOD output on the arty thinking that might make a difference. Still nothing. Should I see the PMOD power on when i plug it into the arty? Im wondering if i have a bad module.
  4. Derp. I deleted the other directories in there and it generated fine.
  5. [Vivado 12-4406] The core container file 'C:/Xilinx/Vivado/2018.3/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_quad_spi_0_0.xcix' cannot be added because it is sitting next to the IP directory 'C:/Xilinx/Vivado/2018.3/vivado-library/ip/Pmods/pmodOLEDrgb_v1_0/ip/PmodOLEDrgb_axi_quad_spi_0_0'. This configuration is not supported. Please move aside the IP directory and retry adding the file.
  6. Oh geez. You are right. Why is that main.c so different? Ok i'm trashing everything back to integrating the PMOD IP into my block diagram. How do I get the XCIX file to unpack? I am using the DA4. But I don't see an ip package for it in the vivado library. It only has DA1. Thanks for your help!
  7. OK. I figured this one out as well. I had my addressing messed up. I was trying to make the data section larger to accept the microblaze project and had changed the base address to something other than 0x00000000. The linker script got all confused. I changed it back to 0x00000000 and moved everything else up in memory. main() is now executing. The oledrgb still isn't working but I think I am missing some stuff in my microblaze setup. I'll see if i can figure it out. Thanks again.
  8. I see in your screenshot you have a MIG. Do I need that? Thanks!
  9. Here is my wrapper file as well. design_1_wrapper.v
  10. So i've actually been able to get it to work. I downloaded the original ip from a link in another forum post. It is ip that says it's for v1 of both of these modules, not sure if that makes a difference. I can generate a bitstream and have been able to export it and program the FPGA via the SDK. I'm now having an issue with not being able to hit any breakpoints once i'm in debug mode. the program counter looks to be stuck doing nothing. see image below. I can start another thread for this issue if need be. Thank you for your reply.
  11. Hello. I'm using a windows 10 64 bit machine. I've followed the getting started with PMODs tutorial and have a microblaze instantiated with my IP in place in the block diagram. I'm working with an OLEDrgb and a DA4. the OLEDrgb is hooked up to JA on the arty a7. the DA4 is hooked up to the JD port. I've downloaded the latest vivado library from github (version 2018.2). I've told vivado where the repository is and I was able to wire it up in the block diagram. I hooked up the correct 50Mhz clock to both of the PMODs. I get a positive design verification but when i try to generate my bitstream file, i get an error saying that Vivado can't find the xci file for the OLEDrgb ip. When I go and look in the folder "path/to/vivado-library/pmodOLEDrgb_v1_0_old/ip" i see the folder that vivado is trying to access the .xci file from but it is empty. instead there is just an xcix file sitting in the ip folder. I've tried enabling the Use ip Core functionality in the ip settings. If i do this, then i get another error when generating my bitstream file that is saying vivado couldn't unpack the ip core for the OLEDrgb. In the "Designing With IP" user guide, it says to enable the core ip functionality for just that module in my sources window. but I don't see the same drop down that it shows in the manual when i right click on my oledrgb pmod. Manual was probably using a different version of Vivado? Any suggestions? Thanks!