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Everything posted by huytergan

  1. Hi again, It's official now that is working on-board as well:D Thanks! But I don't get it why I needed count_next and index_next signals despite variable count and index.
  2. Hi, Thanks for your interest, yes I realized that I did let them increase in first process which shouldn't have been. I deleted both count&index increment over there. Working well inside of simulation. But still nothing on-board. I share my testbench code with you, take a look please. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity rs232omo_tb is -- Port ( ); end rs232omo_tb; architecture Behavioral of rs232omo_tb is signal clk : std_logic; signal rst : std_logic; signal start : std_logic; signal input : std_logic_vector(7 downto 0); signal done : std_logic; signal ou
  3. I want to send 8 bit data from FPGA to PC, 9600 baudrate, 8 bit data, 1 start&stop bit, no parity. I did coded my Basys3 Fpga and connected to PC. By using Tera Term, wanted to see how it works out. But probably something big I'm missing out. I just wrote a transmitter code and somewhere I saw that some people used button&top modules too. Do I need them to see a 8-bit data's ASCII equivalent on my PC? How can I handle? library ieee; use ieee.std_logic_1164.all; entity rs232_omo is generic(clk_max:integer:=10400); --for baudrate port(
  4. I'm working on 2 servos actually, and couldn't adjust their speed, using sg90 servo motors (1-2ms duty cycle, and 20ms refresh frequency). 4 states defined, firstly sweeping horizontal, secondly finding maximum ( as a voltage from pv), thirdly goes through vertical, finally finding maximum of vertical. It was supposed to be like that. After sweeping horizontal, it so quickly passes the part of finding maximum point. Can anyone please help me by taking a look on codes, i'd send the whole file via e-mail which cannot be attached here.