Billel

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Billel last won the day on May 22 2016

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  1. Hello I need exemple design on how to use the DDS compiler IP core with Zynq or Microblaze for the generation of sin and cos waveforms and how to use it in the SDK. can anybody share or guide me to serve this. Thank's
  2. Hi @jpeyron Thank you for your feedback. After searching i found this in the Help of Matlab by typing xlDoc at the command line to open the Xilinx System Generator help documentation. I try this for the Digilent Nexys A7 board and it work properly. best regards, Billel
  3. Hello Is there any possibility to add Digilent board like the new Nexys A7 or Basys3 in the vivado system generator for the hardware co-simulation? thank you.
  4. Thank you for every one What is astonished for me is why clk_out1<= clk; does not work. It is supposed to be the image of clk.
  5. Hi every body I’m working on project where I need to make the system clock externel, start with this simple project. I want to implement a selector between two clocks ( clk and clk1) to the output clk_out0, where clk is the system clock and clk1 is a simple signal that I emulated in this project using the sw1 of the nexys4 ddr fpga board. I use the sw0 of the board to switch between the two clocks. when I select the clk1 ,that comes from sw0, the clk_out0 works perfectly , Unfortunately, when I select the system clock I get a steady signal of 1.8 V , the clk_out1 ,which is supposed to be the system clock, is also at 1.8V. Can anyone tell me what is wrong in the program? here is the vhdl program: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity padd is port ( clk:in std_logic; clk1:in std_logic; selector:in std_logic; clk_out1 : out std_logic; clk_out0 : out std_logic ); end padd; architecture padd of padd is begin process(clk) begin if selector ='0' then clk_out0<= clk; else clk_out0<= clk1; end if; end process; clk_out1<= clk; end padd; and this is the xdc configuration Thanks.
  6. Hi Rana Are you using a Genesys 2 fpga board? If yes, are you using a Microblaze as a soft-core? I have done a current measurement on Genesys 2 FPGA but using a Microblaze.
  7. Hi Sam. thanks for replying, I have do it in the same way and it works.
  8. Hello I'm using the PMODAD1 ip core given by digilent and try to build a project using basys3 FPGA board. first i have create a simple 1 kHz sin wave with +/- 1V amplitude from Digilent Analog Descovery2 and use a PMODAD1 at 50 kHz sampling rate. when I read the integer value from the AD1 I got only the positive values, my question is: 1. Is the exemple given with the IP core is using 12-bits ADC? 2. What should I do to read a positive and negative value from the AD1? I'm using the c programme given as exemple withe PMODAD1 IP core. Thanks.
  9. Thanks again Jon. I will finished my design as you advice me, later I will upgrade to a new version of Vivado. Thank you.
  10. Hi Jon I'm sorry but do you mean that I have to make a copy of the "design_1_wrapper.bit" and rename it to "download.bit"? because I have search inside the project folders and there is only a design_1_wrapper.bit. Another question if you allow me, what is the source of this error? and if I add other blocks in my design, the previous solution still valid? Thank for your Time
  11. Hello again I'm try to use the PmodACL IP i build my project, using Vivado 2015.1 without any error and generate a bitstream. when I try to program the FPGA in SDK I got this error: couldn't open "E:/ Project/project_ACL/design_1_wrapper_hw_platform_0/download.bit": no such file or directory I have check the design_1_wrapper_hw_platform_0 Folder and the download.bit file doesn't exists. How I can fix this problem? Thank you.
  12. Hi Jon Thanks for your help Jon, let me know if there is a new version of the board.
  13. Hi Jon The project is done, it works correctly. why the reset is set 0 in the board file (version C) of the Basys3, while in the old board file (version 1.1) of the basys3 is set at 1 by default ? what I have to do if I want to set the A0 channel and change the sampling frequency? Thanks
  14. Thanks a lot Jon for your replay. I will finish the design and try a simple example in SDK, for the reset, usually I set it active high and its work, is it wrong? Contrary to the design based on Nexys4DDR board, where the set of the reset is a bit diffierent because the reset in the clock_wis block is active low while the reset in the rst_clk_wiz_1_100M block is active high. Thank you.
  15. Hello I want to use the PmodAD1 IP from digilent with Basys3 FPGA Board under Vivado 2015.1. I have followed the Tutoriel "Using Pmod IPs" (https://reference.digilentinc.com/learn/programmable-logic/tutorials/pmod-ips/start). The bitestream is generated but with the following critical warning: - [IP_Flow 19-3298] Detected external port differences while upgrading IP 'PmodAD1_pmod_bridge_0_0'. These changes may impact your design. - [IP_Flow 19-3298] Detected external port differences while upgrading IP 'PmodAD1_axi_quad_spi_0_0'. These changes may impact your design. I have attached with this message the Diagram of the bloc design, for the "ext_spi_clk" of the PmodAD1 Ip I have related to 50 MHz frequency pin (clk_out2). Is there any error in my design? How I can solve this problem? Thanks