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  1. Hi @JColvin Great. Thanks for confirming this. I'll try it today.
  2. @[email protected] Exactly. I was just looking at the site now from following the link you supplied earlier. It looks like a brilliant source of information. Thank you.
  3. Thanks xc6Ix45. So, if I understand this correctly, with this command in the .xdc file, set_property BITSTREAM.CONFIG.UNUSEDPIN <Pullup, Pulldown, Pullnone> [current design] during bitstream generation and subsequent running, all unused pins will be put in to the desired state (pullup/pulldown/pullnone). And it is safe to declare any of these options? I'm just trying to get a feel of how/if the hardware can be damaged by rooky mistakes in the code. But, I'm also hoping VHDL wouldn't include such a command if it were so likely to do damage!
  4. @xc6lx45I predict that the rollout of self driving cars will greatly increase the sale of motorcycles. People generally enjoy driving. The main downside of motorcycling at the moment is human car drivers. I'm looking forward to the day that I won't have to worry about them anymore. Pesky humans! @[email protected] Thanks for the links. I'll take a look at them today. If you have any good advice on common newby mistakes to avoid, I'd be happy to hear them. My current game plan is to just dive in and get my hands dirty, while keeping the magic smoke inside the FPGA! I've already seen you both are qu
  5. I did consider going in that direction. Alas, my moral compass prevented me from a career in making a fortune from the losses of others. Physics is about rules. Finance is about breaking them and getting away with it! 😉
  6. " It's meant to be used, if it fails it fails and most likely there's not a thing you could have done to change that (other than putting it into a locked closet)." Good advice! But the 7-segment LEDs didn't light up at all previously unless intended. So I tested one of the previous project that *does* use the 7-segment display, and that actually worked, with the unused segments fully off. So I think you're correct about the unused pins in my other projects causing the faint glow (although they didn't do that initially). And strangely, (while I'm writing this), testing one of my other
  7. Hi all, I have the same symptoms as the OP posted here: I have been following tutorials, implementing simple designs like Adders, Shift-Registers etc. All was going fine until today when I implemented a Counter. The synthesis, implementation and bitstream generation succeeded, albeit with some warnings. When I flashed the FPGA, the 'program complete' LED lights up, and the 7-segment display is faintly lit. The project doesn't use the 7-seg, it displays the count in binary on the LED above the switches. The Info at the end of the programming says: INFO: [Labtools 27-
  8. Just joined the forum and thought I should keep with tradition and say Hi! I've got a BASYS3 board (awesome piece of kit) and I'm about 1 week in to teaching myself VHDL after completing a PhD in experimental particle physics and realising that there's not a lot of use for it in Northern England! Best regards. Miakatt.