Hong

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  1. Hong

    Vivado sysnthesis fail..Pcam

    ERROR: [Synth 8-485] no port 'axis_data_count' on instance [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/LLP.vhd:578] ERROR: [Synth 8-485] no port 'axis_data_count' on instance [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/LLP.vhd:578] ERROR: [Synth 8-485] no port 'axis_data_count' on instance [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/LLP.vhd:111] ERROR: [Synth 8-285] failed synthesizing module 'LLP' [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/LLP.vhd:79] ERROR: [Synth 8-285] failed synthesizing module 'MIPI_CSI2_Rx' [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/MIPI_CSI2_Rx.vhd:77] ERROR: [Synth 8-285] failed synthesizing module 'mipi_csi2_rx_top' [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ipshared/1a11/hdl/MIPI_CSI2_RxTop.vhd:131] ERROR: [Synth 8-285] failed synthesizing module 'system_MIPI_CSI_2_RX_0_0' [c:/fpga_work/Zybo-Z7-20-pcam-5c-master/src/bd/system/ip/system_MIPI_CSI_2_RX_0_0_1/synth/system_MIPI_CSI_2_RX_0_0.vhd:112] --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:23 ; elapsed = 00:00:26 . Memory (MB): peak = 762.250 ; gain = 408.602 --------------------------------------------------------------------------------- RTL Elaboration failed INFO: [Common 17-83] Releasing license: Synthesis 86 Infos, 123 Warnings, 0 Critical Warnings and 8 Errors encountered. synth_design failed ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details INFO: [Common 17-206] Exiting Vivado at Sat Dec 22 12:16:05 2018... This is the part of log file.... What is the problem??? Plz let me know how to fix this error.......thanks
  2. My Vivado Ver 18.3 and every time occured error like picture... My board is Zybo Z7 20 + Pcam... I already did it all like forum solution. Plz let me know how to solve it. I did it below steps. 1. Download the latest version of the Pcam 5C Demo project from https://github.com/Digilent/Zybo-Z7-20-pcam-5c, in zip format. 2. Use the vivado library zip file (which includes the D-PHY and CSI-2 IPs) you previously downloaded from https://github.com/Digilent/vivado-library/tree/feature/d-phy, or download it again. 3. Unzip the two zip files, put the vivado library in its folder under the repo folder. 4. Run the create_project.tcl script from Vivado 2018.3. 5. In ´╗┐the project block diagram, double-click on the MIPI_CSI_2_RX_0 IP and deselect Debug Module. Press OK. Save the project. 6. HDL Wapper -> Generate Birsteam. Always result is same, so I can't work anything.................. thanks