BenWillis

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Everything posted by BenWillis

  1. @jpeyron After two weeks of fiddling, my project partner and I got your block diagram project to work! We did so by eliminating any discrepancies we could find between the implemented schematic from your block diagram with the implemented schematic of from the top file. Specifically we made the following changes: 1.) Used the pynq-z1 board file from here. 2.) I changed the i2c interface you outlined to the one specified in the top file of the project from github. The end result was that I got a schematic in the implemented design which exactly matched the schematic generated from the top file. Thank you for your time and efforts! I'm sure I'll be back with more questions later. Cheers! Ben
  2. @jpeyron Thank you for all your help sir! This has been a great learning experience. I successfully got the top file project to work with the constraints file to work on my PYNQ board as well. I will not be able to test your project until after the holidays but my project coworker may do so in the next few days. I will post here if the test is successful. Again thank you for your help and you'll hear from me! Ben
  3. @kwilber no, no particular reason. The design posted here was advertised to work and didn't include any reset functionality so I left that out. You thing driving the arst ports of the block diagrams is a good idea?
  4. @jpeyron @kwilber I've changed my above constraints and block diagram to the following Block diagram constraints
  5. I duplicated the project that @jpeyron linked to. I did my best to duplicate everything in the first response to that post. Here are screenshots of my design. constraints block diagram dvi2rgb settings rgb2dvi settings clock wizard 1 clock wizard 2 Here are the critical warnings and errors I received when synthesizing and implementing the above design critical warnings errors
  6. Hello, I am trying to make an HDMI passthrough application on the PYNQ-Z1 board using the dvi2rgb(1.9) and rgb2dvi (1.4) IP blocks from this github repo. Here are the technical details of my tools: Vivado 2018.2 PYNQ-Z1 board (part xc7z020clg400 - 1) (Got the board file I’m using in vivado from this webpage Dvi2rgb v1.9 Rgb2dvi v1.4 Here are some images of my project: Constraints Block Diagram clock wizard settings dvi2rgb rgb2dvi Long story short, the application doesn’t work when I use it between my laptop (Lenovo Z710 Ideapad running Windows 8.1) and my TV (Toshiba 49L420U with dimensions 1920x1080) After consulting a lot of posts on this website, especially this one and this one, I’m still not sure about what the magic formula is to get these IP blocks to work. The posts don't seem to be addressing the problems I'm having with this design, but rather making changes to the specific implementation of the project. They were all older versions of the IP blocks and vivado, and they were using different boards, so those factors may have contributed to why those examples didn't work for me. I’ve reduced my critical warnings down to three, which are the following: 1.) Timing: i get the following timing warnings after running implementation 2.) Set_property expects at least one object a. I get two of these, for the two constraints listed at the very bottom of the constraints I showed in the first image above. How can I write these constrains such that Vivado will recognize them and won't throw a warning? I read from the posts I mentioned earlier that timing requirements may throw a critical warning but the design will work anyway, but I haven't had the same fortune. So has anybody here gotten their design to fit timing and create a working project? If so I'd love to know how, and if you failed timing but still got the project to work, what did your timing analysis look like? As can be seen in the block diagram, I pulled the aPixelClkLockd signal out to an LED, which is an active high signal. But I haven't gotten this signal to be high, so obviously that's a problem. If the clock recovery block in the dvi2rgb IP can't get a lock on the incoming clock signal, does this mean that the project is not properly constrained, or does this mean that the IP block won't work with my laptop? I read a lot about DDR signals, and I believe that I set those up correctly in my block diagram and constraints file. But I didn't understand what hpd signals did, and I don't know which block diagram they are supposed to come from. Any help here would be greatly appreciated! Best, Ben