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  1. Josef

    SPI slave in VHDL

    OK, thanks. Information provided by you is enough for me. And it's what I looked for. Best regards Josef
  2. Josef

    SPI slave in VHDL

    Thank you for answer. OK, I met with warning about clock - clock dedicated route in past time in another designs, paradoxically not in this. I standardly used system clock and timing derived from it in another designs, but in SPI slave design I hesitated about using system clock or not and the reasons they made me uncertain was accurate detection of falling edges of signals (SCK and SS) and also some ICs what communicate by SPI or some variants of it don't have own system clock (for example R2R DACs), but also there can be internal RC oscillator, internal XTAL, or something like that.
  3. Josef

    SPI slave in VHDL

    Thanks for your answer. My idea was to make own component SPI slave what can be by user setup into all 4 modes (combinations of CPOL and CPHA), also I added as in posted code CSPOL for setting what CS level is idle. Yeah, I know that my implementation is not usual as other implementation is (other implementation makes single component for all SPI, use one register what is shifted by SCK, etc.) but I can do with parallel data bus everything in higher entity and so on. I didn't try to think about automatic detection of mode by transaction, but this is also interesting idea, what I maybe try
  4. Josef

    SPI slave in VHDL

    Hello everyone, I have question about possibility of realising SPI slave on FPGA using VHDL. I know that there is some open cores, free SPI libraries in VHDL, etc., but I think that do it own way gives experiences. When I coding SPI master, it was a little bit trivial, but now I try to solve SPI slave and getting into some trouble. My question is about how is the best practice for detecting falling edges of SS (in code below CS) signal and then SCK signal for setting MISO signal, when I am using mode 0 (CPHA = 0 and CPOL = 0). I saw some sample codes of SPI slave in VHDL where a
  5. Hello, can anyone tell me how I can check if any elemenent (e.g. switching matrix, etc.) of ArtixA7-35T is not broken? I have accidentally wrote to my Basys3 board bit file created for Arty... I have tested it with onboard demo (LED display, switches, LEDs and buttons) and everything look ok, but I have read that bit file programming internal switch transistors in switching matrix and there can be something damaged. Thanks in advance for any response Best regards Josef
  6. Hello @jpeyron Thanks a lot. I only found that DDR memory on revision D have resistors on data lines what missing on revision C, memory type is the same. Does it mean that DDR on Arty wouldn't work on same high speed as on Arty A7? Or I overlooked something in schematic? Best regards Josef
  7. Thanks for describe of troubles. So if I understand, problem is only when user access the flash from design (or own software in computer) and leave the memory in unknown type of communication SPI or QSPI/XIP and next time you want to download some data to this flash from computer, am I right? So driver from Digilent uses one type of communication (I guess, if you mentioned about high speed flash controller type SPI) and if I access the flash from design and leave the flash in QSPI/XIP, Vivado HW Server can next time have problem with download design to flash? Or standard download programs impl
  8. So problem is in driver in PC, right? I looked once again and I think that newer board can also fit 100T version of Artix (some ceramic capacitors are also near of FPGA package diagonal on top side of board, what I doesn't have on my board). Can I ask for problem with flash, how you Dan found problem with memory power-on reset? What are symptoms and what steps I can also get into this trouble? Best regards Josef
  9. So if I understand Dan, Arty (revision C and earlier) have a flash config memory from Micron (IC3 or IC4 location) what have internal design problem caused by sometimes problematically power-on reset? So if I want Arty without problems, I have to exchange memory from Micron (N25Q128A13ESF40) to memory ideally from Spansion (I only found Cypress S25FL128SAGMFV003) on board, am I right? Best regards Josef
  10. Hello everyone, I searched for something information about programming interface for DDR3L on Arty board what I bought and I got on page - reference manual for Arty board and there is information saying that Arty reference manual is for revisions A - C of board. I have looked on my revision and on board is printed REV. C. Before I met this information I used schematics, reference designs and et cetera files from page Arty A7 and it seemes that all works fine. So I have two questions. If I downloaded materials for Arty A7, must I download materials for Arty, if I have revision C, or files
  11. @[email protected] Ah, in implementing memory controllers I don't have any experience, so it can be challenge implementing also SRAM controller and I think also DDR controller (I'm afraid of sensitivity both clock edges what I currently can't imagine how I will implement something like this). At SDRAM I only looked for access times. I have last question about generating VGA image. Can HyperRAM on two PMODs works on higher resolution? Space I think have enough (I think 8 MB), able working on 100 MHz, so resolution 1024x768 256 colors will be also possible also on Basys 2 with increase of pixel clock, am
  12. @[email protected] Thank you for your response. I like your 3rd idea, so the solution generaly can be using a DDR memory, is it right? And what SDRAM as I mentioned above, could be also useful? Best regards Josef
  13. Hello, thank you for your answer. I found also SDRAM IS42S16400J from Integrated Silicon Solution Incorporated. This memory has access times few nanoseconds (max 10ns). Do you think that this could be the way? Thank you in advance for your response Josef
  14. Hello everyone, I am a little newbie to generating VGA from any development kit, today I made a simple VGA image generation working on Basys 2 board with Spartan 3E-100. In code I'm currently using construction with IF sections for setting pixel colors at the required coordinates, but I think that this is not the best practise, because images is in this case programmed like in a ROM... So I would like to ask what is the best practise for storing images in Spartan 3E-100 next intended for displaying by VGA? I would prefer to have one component driving displaying to VGA from something like