• Content Count

  • Joined

  • Last visited

  1. Hi Sam Ok, that should work perfect for me. Thx a lot for that information. Regards AHz
  2. Hi Andrew Thanks for your answer. My problem is that i have no control over the integrated JTAG controller. Particular i don't know when it is driving. There are JTAG controller in the field that 3-State their outputs when they are inactive. Others keep TDO, TMS & TCK at logic0 (seen at a kind of "on-board programmer" - not really a "official" JTAG controller). I'm not sure what is 1149-1 conform behavior. Moreover im not sure what is Xilinx conform here Did i mention that i hate undocumented hardware blocks on lab-boards? ^^ Regards AHz
  3. Thanks for your help. I'm waiting curious :-) Regards AHz
  4. Hi all I'm still using a Spartan3e starter kit for various issues (it's aged but still very usefull). For my current project i need to program the Spartan using an external uP that i want to connect to the connector for extended JTag (J28). Now i become unsecure how this should work. The s3e1600 board provides an integrated JTag programmer. Unfortunally it is not documented in the schematic's since it is an Xilinx proprietary design. Moreover J28 does not provide anything like the PGND signal, found i.e. at the Xilinx platform cable USB II. Hence the S3e1600 board can't detect a connected JTag adapter. I ask myself if this cause any problems when i now use a second (!) JTAG master (via J28) to drive the JTag chain. If i interpret the given schematics correct then i would assume that the integrated JTag controller would be in parallel to J28 (but as i said: this is not documented) which would be asking for trouble . Can anyone provide some help for this ? Thanks in advance Regards AHz