Sami Malik

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  1. Hi, Currently I'm working on a project in which I want to transfer 1MB data from PS to PL using BRAM using custom IP. I receive correct data at PL whenever I send data less then 32 bits from PS to PL but when I send more bits from PS, I'm unable to receive even a single bit. is there any clock issue as I'm using clock of PS for my custom IP or their is any other problem? Regards, Sami
  2. Hi @jpeyron Thank you sir for your time. If you are going to make a project then let me try to explain it once again. Actually sir I have written a verilog module(VGA.v) which will be controlling my vga port. I also have some data in my PS section of ZYBO, that I want to transfer to my verilog module(VGA.v). For this purpose I am transferring data from PS -> dual port BRAM -> my custom IP. Basically I am using a custom IP so that I will take the data coming from PS section and Transfer it to my verilog module(VGA.v) by instantiating my IP to my verilog module. Regards, Sami
  3. Hi @jpeyron I think I can't explain the problem clearly of you don't understand it anyways thanks alot for your time and reply. Regards, Sami
  4. Hi @jpeyron I am just transferring data of dout to my verilog module using instensiation of my verilog module in top level Wrapper but I think I don't know the exact procedure to do so as I have attached above my work that I have carried out until now. In above attachments I showed that I want to switch on LEDs to start from basic but changing xdc file will not lead me to my solution. Thanks.
  5. Hi @jpeyron, Sir I don't know the exact procedure to instantiate my verilog module in wrapper. Actually sir I want the data coming out of dout to be utilized in my main verilog file. For this purpose I thought let's start from basic which is to switch on and off the LEDs with the help of data coming out from dout. But changing the xdc file for my purpose will may be not help me out. I want to instantiate a verilog module in wrapper which will be doing the same task. My all approach to do so is given above even my verilog module. Maybe now you will be able to help me out more accurately. Thanks for your reply sir. Regards, Sami
  6. Hi @jpeyron yes sir sure, they are attached below. Zybo-Master.xdc New Text Document (11).txt
  7. Hi i am working on a project in which I have to take output from bram and turn on leds on ZYBO using custom IP. So far I am able to write on BRAM from PS section and read it from PL section of ZYBO with my custom IP. I want to connect the data coming out of my custom IP with my on board LEDs of zybo without interfacing AXI_GPIO. For this purpose I set the output of my custom IP as external and wrote a verilog module in which I'm trying to get data of my external port on the basis of which i am switching on and off the LEDs by instantiating it with design_wrapper. But it is giving the error on my external port while generating Bitstream. How can I overcome it and is there any alternate way to do that? screenshot of my design errors, verilog module are attached below. Regards, New Text Document (11).txt
  8. Ok sir I will use this xparameters.h in my project and I'll inform you after testing it. And I also saw those examples but didn't test them before. I will also test them and will get back to you if I get any problem again. Thank you sir you are really helping me out and giving me your precious time.
  9. Sir I have tried to rebuild it but nothing changed. So according to you 0x00000000 is the base address of Bram. Right sir? So I have to use this address to read and write to BRAM? Thank You.
  10. Sure sir. Both screenshots are attached below but I think there is some sort for generating linker script page. Its saying that no application project is selected but you can see on the left side of window i have selected helloworld.c application project. I think I don't understand the error or I don't know how to overcome it. Thank you
  11. Hi I made a block design in which I have connected BRAM with PS in vivado 2014.4. Then I created hdl wrapper and then generated an output product and then generated a bit stream and then exported it to sdk. But when I opened it in sdk my .hdf file is updated correctly but in bsp file, xparameters.h is not getting update and showing me wrong values of base and high address of my BRAM. In vivado base address of axi_bram_ctrl_0 is 0x40000000 but xparameters.h in sdk is showing me 0x00000000. Screenshot of addresses is attached. I have repeat the whole process of making a block in new project and exporting it to sdk but nothing changed. Regards,
  12. Thank you sir, I have checked the manual and thread. But sir I want to read and write to BRAM using verilog how can I achieve it? Is there any way to make an array whose starting address in memory will be same as the starting address of BRAM(0x4000000)? Basically in this way I think I will be accessing the BRAM. Another thing is that can I assign values to componants directly in hdl_wrapper.v file of my block diagram? I was trying to do so but it failed in generation of bit stream. I was doing this thing for the same reason that is to write and read data of BRAM using verilog...
  13. Block diagram of what I have done so far is given below. I don't know whether its correct or not. Please correct me if I am wrong.
  14. Hi, I have made the block diagram of BRAM and populate it from PS section of Zybo. I have made the PORTB of BRAM as external. Now I want to read this BRAM from PL section but I don't know how to read it using verilog code. Do I have to make changes in design_wrapper.v of my block diagram and then I have to do some instantiation in my main.v or there is any other method to do so? Regards, Sami