Abdul Qayyum

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  1. Like
    Abdul Qayyum reacted to jpeyron in UART Communication of Zybo via Bluetooth.   
    Hi @Abdul Qayyum,
    I am not directly seeing anything wrong with your FSM. Here is a UART RX TX verilog module and here that should be useful for your project. 
    best regards,
    Jon
  2. Like
    Abdul Qayyum reacted to jpeyron in Reading Data From BRAM of Zybo but receiving data is garbage.   
    Hi @Abdul Qayyum,
    Glad to hear you were able to resolve the issue. Thank you for sharing what you did to resolve the BRAM issue.
    thank you,
    Jon
  3. Like
    Abdul Qayyum reacted to jpeyron in Reading Data From BRAM of Zybo but receiving data is garbage.   
    Hi @Abdul Qayyum,
    On page 41 of this PDF  here is some good SDK code to start from. In the attached code nothing has been placed in 0400c0000. Also  wouldn't you want to use %d instead of %x?
    cheers,
    Jon
  4. Like
    Abdul Qayyum reacted to Notarobot in Reading Data From BRAM of Zybo but receiving data is garbage.   
    Hi, Abdul,

    Here are my notes/recommendations:

    1. Open your block diagram in Vivado where you created BRAM configuration and then check the address editor. You should see whether the BRAM address was assigned. If you find assigned see axi_bram_ctrl_0 OffsetAdress and the Range then the BRAM was created and mapped to the memory.

    2. Writing and reading from BRAM requires a clock signal. Check Xilinx templates for BRAM which you can access inside the Vivado. I am not sure that the code you've used to write into BRAM does anything.

    3. You don't use an absolute address in your HDL when BRAM created in Vivado. Vivado maps the address 0x4000_0000 to 0. So you can start from the address 0 and it will be the lowest address of the BRAM. If your don't use Vivado then you will need to define your block in HDL and include addresses, and many other parameters.

    4. The C-code in SDK should use BRAM address from the file parameters.h. You just need to use XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR as the begining of the BRAM address space.

    5. You can treat BRAM as RAM meaning that all read/write operators are the same.
    For example you can copy BRAM content into the RAM:

    for(i = 0 ; i < BRAM_SIZE ; i++)
    *(destination + i) = *(source + i);
    where source = XPAR_AXI_BRAM_CTRL_0_S_AXI_BASEADDR

    Disclaimer: always read documentation, whatever you find on Internet might not be correct.

    Good luck!
  5. Like
    Abdul Qayyum reacted to jpeyron in Pmod BT2 is receiving '0' and '1' but i am unable to use this data in my Verilog code.   
    Hi @Abdul Qayyum,
    Glad to hear that you were able to move forward with your project!
    thank you,
    Jon
  6. Like
    Abdul Qayyum reacted to jpeyron in Pmod BT2 is receiving '0' and '1' but i am unable to use this data in my Verilog code.   
    Hi @Abdul Qayyum,
    Have you verified that the HC05  bluetooth communication is working with the Arduino?  The attached arduino code looks different than i expect. Here is a arduino tutorial for using the HC05  bluetooth. Aslo have you though about using the Pmod BT2 IP Core in the Vivado Library. Here is the digilent IP Core tutorial.
    thank you,
    Jon
     
  7. Like
    Abdul Qayyum reacted to jpeyron in Pmod BT2 is receiving 0 and RX is connected to led0 but led is permanently on   
    Hi @Abdul Qayyum,
    You should be able to use the Pmod BT2 in the PL without and issue. I linked multiple VHDL projects above that use the Pmod BT2 that should be good references for your project.
    thank you,
    Jon
     
     
  8. Like
    Abdul Qayyum got a reaction from jpeyron in How to Configure Pmod BT2 as a Slave with HC05 which is connected with arduino   
    Thank you Sir  
  9. Like
    Abdul Qayyum reacted to jpeyron in How to transfer signal to Programming Logic (PL) of Zybo from Pmod BT2?   
    Hi @Abdul Qayyum,
    Here is a xilinx forum thread that discusses this topic.
    thank you,
    Jon