yottabyte

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  1. Thank you for answering! Isn't the Petalinux support be done by Digilent -as you also say in 1.? But I noticed in the Xilinx doc you showed me that there is no BSP anymore in the new VITIS developewment flow. The Vitis Platform Project would contain Zybo-specific information about onboard components, right and is needed for any kind of developement, right? So does Xilinx publicize Platform Projects (if you say it's a X. question)? If don't want to wait for a couple of months, I have to install 2017.4 toolchain, right? Or is it worth it installing Petalinux 2019.2 (and Vitis)
  2. Hi sorry in advance for a question that I maybe should be able to answer by myself using Google. I really did but still I don't know. The reason therefore probably is that I'm just about to get in touch with Petalinux and Zynqs PS at all. I never did before. So, do I understand correctly that with a Zybo Z7-20 it doesn't make sense to update to Vivado 2019.2? The most recent version of Petalinux for exactly this board is 2017.4. Software on this shouldn't or cannot be developed by using Vitis instead of SDK. Is this correct? Vivado 2019.2 and SDK are totally incompatible, this
  3. Thank you @xc6lx45 ! Really interesting lesson... The way I see FPGA hardware seems to change a lot in this moment, -in a way I like a lot So do I understand you correctly, that this, , means, that damage can be caused by high current or an excessive change of voltage in a short time BUT NOT by relative big voltages themselves, as long as they don't change too quickly? So with voltages that are "just" a few times as high as they are supposed to be, like 10V maybe for example, diodes on chip will keep away what is too much? (-reliably if serial resistance provided?) But
  4. Hi, apparently it is easy to damage something by playing around with the XADC-port (of a Zybo-Z7 in this case). I want to read the charging curve of a capacitor. How I thought this could be done I simulated in LTSpice: 300mv are much less than the maximum 1V and I added R5 and R3 because there are no preresisitors inside XADC-ports. I guess this way my hardware should survive the first time converting an analog voltage curve into digital value. But I'm, just guessing so the two questions I have about this are 1. Is this safe? 2. Is there a better way to do this? a
  5. Hi @JColvin, my question was about choosing the correct Zynq in Vivado when creating a new project for the Zybo Z7-20 (see attachment). This exact label with -1, -2 or -3 at the end you can't find anywhere. But all you have to do (and what probably anybody does anyway, besides me) is downloading the Digilents board files here, so the Zybo Z7 shows up in the list of boards. I thought this is not worth a thread. But maybe there will be another user who won't just open up another tutorial that gives the information about the board files, you're right. Thank you @xc6lx45
  6. hi @xc6lx45, oh, thank you a lot for explaining me these facts - very interesting and of course conclusive. I will order the bigger Zybo-Z7 from trenz next week. In this case saving 50€ is obviously not worth it. I already put some stuff on ebay for this. I'm really glad I didn't find out about these things afterwards. 👍
  7. Hi @jpeyron, thanks for your answer. This is exactly information I am looking for. To be honest, first thing I thought was: Of course it's a Digilent-demo which doesn't fit on the bargain-board... 😉 I'm just kidding (better to be mentioned, the smileys are really small here). Anyway, this is interesting. What does make a project like this so voluminous? Is the reason something like, that there are equivalent modules for every pixel? Until now, it doesn't seem to be recommended to save the 50€/60$ difference of the Zybos - even for people it's painful for. This example doesn
  8. Hi, at the moment I'm pretty sure my board of choice will be a Zybo Z7, but I'm still not sure about which one of them. If a bigger FPGA is needed depends more on the kind of projects rather than the size itself, that's why I can't just simply extrapolate, how much logic I will probably need. Could you please describe me somehow, for which kind of projects the PL of the Zynq-7010 could be too small and the greater Zynq-7020 would be recommended or needed? Or could you maybe give me some examples of projects, which wouldn't fit into a Zynq-7010? Zynq 7010: 28K logic cells Zy
  9. Hi, not a long time ago, I got in contact with FPGAs/Verilog and noticed, I like it. After having some fun with a Basys2, I want to get into SoC now. Of course first of it all there is the decision to make, which board to buy. After quite a few hours of research there are two boards left: Zybo-Z7 and the ZedBoard. Sometime probably I will do something with video to do something which takes advantage of parallelism. I'm still not clear about the advantage of the Zybo's Pcam adapter. I know the maximum bandwidth through Pcam is higher than through ZedBoards highspeed-Pmod. But isn't the lim