• Content Count

  • Joined

  • Last visited

About oliviersohn

  • Rank

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. oliviersohn


    @D@n I don't have an exact expectation of speed, since I'm merely doing that to learn and to get a sense of what developing for an FPGA looks like. Your answer kind of helps in with that respect! Doing the brute force convolution is an intermediate goal, but the end-goal of this first project is to do fft-based convolution, since it uses less operations (I implemented a 0-latency convolution using ffts on a CPU, in C++, now I'm trying to see what it takes to do it in hardware). I guess I'll start with very simple things first like making leds blink Olivier
  2. oliviersohn


    @D@n I guess the memory controller needs to read 8 times from the memory bus before delivering the content (hence the 20 cycles from request to response), and maybe I could do some pre-fetching stuff to hide this latency ... If the MIG runs at 82Mhz (which makes sense since it is roughly the memory bus frequency divided by 8 ), is it possible to have a slower clock for the MIG and a faster one for the rest of the design?
  3. oliviersohn


    Hi @xc6lx45, thanks for your replies! My concern was about burning the sticker due to FPGA heat, not burning the FPGA itself. But thanks for the link! I finally just removed the sticker. I asked the question on stackoverflow regarding brute-force convolution a few days ago (just before buying the board actually): https://electronics.stackexchange.com/questions/406295/brute-force-convolution-reverb-in-fpga and someone answered with a back of the envelope calculation, where external RAM is used instead of block RAM, but in the calculation the speed of the RAM bus was not taken into account. I see that on the Arty A7 the 16-bit bus is @ 667MHz, which is roughly the same speed as the FPGA clock, but at each FPGA clock I would need to read some hundred coefficients from RAM so it's not going to work, as you said the RAM is the bottleneck here 😕 Anyway, it'll be fun to see how far I can push this! I didn't understand what you meant by the need for a preprocessing step, do you think of truncating the response?
  4. oliviersohn


    Hello! I'm a FPGA newbie, I just purchased an Arty A7 from Amazon (the 35T version and received the 100T version - lucky me !!) and will be trying to run an audio convolution reverb on it... Well, at least that's the goal, first I'll try to power it on I guess I had a question regarding the sticker that's on top of the FPGA chip: I assume I should remove it, in case it gets hot, but didn't see any instruction to do that anywhere, is there a documentation I've missed? Cheers, Olivier