So let me shoot in the dark and ramble and see if it helps clarify your question. There are many ways you can design things on a Zynq.
You can create state machines like you did before on the Spartan 6, making logic just like before that will work without a CPU. Indeed, you can still control I/Os like before if you want. The AXI GPIO core may be nice, but it is certainly not required.
You can create AXI slave cores. Anything you create with a slave interface can be connected to the ARM in the Zynq and can interact with the ARM. This is typically very useful for controlling peripherals from the PS. You would write software commands to interact with your device, and off you go. This might be the easy way to interact with the AXI GPIO, but it is by no means the only way. There's also a discussion to be had about where the O/S / Application division will be within your software and how to write a proper device tree entry for IP cores that will be controlled from Linux.
You can also create AXI master cores in PL. Your AXI masters can then be used to drive AXI slaves. So, for example, if you wanted to control the AXI GPIO as a state machine on board, all you would need to do is to connect an AXI master to it to do so. This would apply to any DDRx SDRAM as well. Yes, it is possible to connect an AXI master to multiple slaves, this requires an interconnect however.
Which method you choose is up to you, the designer, and the specific and particular needs of your project. For example, logic is limited but fast, whereas software tends to be abundant but not nearly as fast. Further, most CPU software will produce (fairly) unpredictable timing, where as timing can be tightly controlled from the PL.
Hopefully these ramblings will at least suggest where the conversation might go next.