I have a verilog/Vhdl design that reads the input from a digilent pmod analog to digital converter (AD1) and send the output to another digilent pmod (digital to analog converter, DA2 or DA3). I checked that design on three different FPGA (Spartan6 lx9, Spartan 3 Starter kit and Zedboard). The design works fine on the above FPGAs. Now I decided to upgrade my design to run on a ZYNQ 7020, but it doesn't work. If the synchronization frequency is set to 20 MHz for example, I cannot see the clock to the corresponding pmod of the zynq board. If I slow down the frequency, I can see the clock but its amplitude is Small (around 200 mV compare to the reference voltage of 3.3 V). Moreover, I don't know why, but the clock signal seems to have an offset greater than 1V. I want to know if somebody before me faced the same problem? If yes how did you solve it? The second question I would like to ask is to know if Digilent Engineers checked their pmods on the Zynq 7020? If yes, could you please provide us with a template design as reference to check on our board? Thank you for any suggestions.
I went ahead and tried my suggestion and it worked. I used a razor blade to cut the pin on the transistor with the arrow, and the SCLK signal on the corresponding Pmod pin looks great now. This does mean that the LED is unconnected, but oh well. I'm not sure why Xilinx designed their board like this, but this fix works. I attached a pic of which pin I cut to make it work.