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herve

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Everything posted by herve

  1. I am working with the digilent Zmod-ADC1410 (14 bits and 105 MSPS) which features the AD9648. According to the AD9648 datasheet (Timing section), it is stated that the AD9648 provides latched data with a pipeline delay of 16 clock cycles. Is it possible to bypass or reduce that pipeline delay? I would like to get the sample data as soon as possible (let's say in the next clock cycle, after sampling the adc input ). My feeling is that the pipeline delay (16 clock cycles) will introduce a considerable phase lag before the gain drop of 3 dB. This could limit the use of the full potential (Bandwidth) of the ADC. Is that pipeline delay configurable via some registers? Thank you!
  2. Thank you guys for all your help and assistance. In the end, I think the best solution would be to design a custom DAC that meets my needs, even if it takes me away for a moment from my main goal. I also think that if Digilent ever came up with Pmod ADC/DACs with a sample rate greater than 2 MSPs, this could be of interest to many people. Thanks! H
  3. This is the absolute group delay and not the delay uncertainty. If it was the delay uncertainty, yes I could mitigate it by interpolating the samples. Thank you. H
  4. Hi xc6lx45, A conventional audio codec will be insufficient because I have to control the delay of my processed signal with a precision of at least 0.5 us (2 MHz). Which means that if my DAC has a sampling rate lower than 2 MSPs, I could not reach the 0.5 us required! Thanks! H
  5. Hello everyone, I am looking for an ADC and a DAC of at least 2 MSPs and a resolution greater than or equal to 12 bits. I do not want to use ADC or DAC with an FMC type interface (I do not have enough free pins on my FPGA card). A serial type interface (SPI) would be nice. Are there PMODs that have these characteristics? If not, can you recommend an ADC / DAC with these characteristics (> 2 MSPs and> 12 bit resolutions)? I have to process signals of frequency <= 10 kHz and send them to a DAC with a resolution of at least 12 bits and an acquisition speed of at least 2 MSPs. Thank you! Regards H
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