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Everything posted by herve

  1. @xc6lx45 Thank you! I will look at the open-source xc3sprog utility. @Dan Thank you! I know the vivado option to create a * .bin file :) I will use a hex editor to open the bin file and read its contents. Then I will try to transfer this content into the flash and check if the fpga can be configured from this flash memory at startup. Herve
  2. Is it possible to write a VERILOG / VHDL code to download the programming file (fpga bitstream) to the hardware device (for example an SPI flash memory)? I'm asking this, because I would like to transfer a bit stream into a spi flash memory, which will then be mounted on an fpga card for boot and configuration. I have already written a few lines of code to write, read, and erase the contents of the 32 MB NOR flash memory (PMODSF3). I tested my code and it works without problems! However, how to read the bitstream, before writing it to the flash memory? Do I only need to transfer the bitstream into flash memory or do I have to add a header and a footer in the memory before and after the transfer of the bitstream file? Have you ever worked on a similar project? N.B: I am using a Xilinx FPGA (Artix-7) on a customized board. I would like to find an alternative solution to the Xilinx hardware manager to program the SPI flash. Any ideas, feedbacks and suggestions are welcomed! Thank you Hervé
  3. Thank you guys for all your help and assistance. In the end, I think the best solution would be to design a custom DAC that meets my needs, even if it takes me away for a moment from my main goal. I also think that if Digilent ever came up with Pmod ADC/DACs with a sample rate greater than 2 MSPs, this could be of interest to many people. Thanks! H
  4. This is the absolute group delay and not the delay uncertainty. If it was the delay uncertainty, yes I could mitigate it by interpolating the samples. Thank you. H
  5. Hi xc6lx45, A conventional audio codec will be insufficient because I have to control the delay of my processed signal with a precision of at least 0.5 us (2 MHz). Which means that if my DAC has a sampling rate lower than 2 MSPs, I could not reach the 0.5 us required! Thanks! H
  6. Hello everyone, I am looking for an ADC and a DAC of at least 2 MSPs and a resolution greater than or equal to 12 bits. I do not want to use ADC or DAC with an FMC type interface (I do not have enough free pins on my FPGA card). A serial type interface (SPI) would be nice. Are there PMODs that have these characteristics? If not, can you recommend an ADC / DAC with these characteristics (> 2 MSPs and> 12 bit resolutions)? I have to process signals of frequency <= 10 kHz and send them to a DAC with a resolution of at least 12 bits and an acquisition speed of at least 2 MSPs. Thank you! Regards H
  7. herve


    @xc6lx45 Thank you for your answer and the link! Regards, H
  8. herve


    Hello @BogdanVanca Thank you for your reply with part numbers. There is still one opened question without answer. I still need to clarify if it is possible to drive the enable pin at a rate higher than 2 kHz? If yes, what is the highest rate? I looked through the datasheet, but I there is no details about the highest rate one can drive the enable pin. Thank you Kind regards, H
  9. herve


    Hi, I have a couple of questions regarding the PmodHB5. How fast can I control the Pmod Hb5 activation pin? In the reference manual (page 2),there is an example with a 2 kHz and 50% duty cycle. Is it possible to drive that pin at a rate higher than 2 kHz? If yes, what is the highest rate? How fast can I switch on and off the transistors of the Pmod Hb5? Is it possible to have the datasheet of those transistors? Thank you.
  10. Hi Dan, I do not know if I should continue to interact with you on this forum or should I continue on the FPGA forum? Anyway, I have recently purchased a Digilent PmodSF and I started to write a verilog module to interact with that memory. I successfully implemented the read identification command based on the Micron M25P16 datasheet and was able to read the manufacturer and device IDs (0x2020 15). I also implemented two other modules based on Micron M25P16 data sheet ("write enable" and "read status register"). However, after executing the "write enable" command, the output of the "read status status" was all the time null, ie 8'b0000_0000 instead of 8'b0000_0010. I'm stuck at this level, because if the "write enable" command is not able to set the "write enable latch" bit to 1, I could not write or program the memory. Could you please provide me a template that I could use to quickly verify that memory? I am working with a Spartan 6, Basys3 and zynq FPGAs. The only design that I found in VHDL is based on a Nexys3 and it requires a USB controller port on the host board. Unfortunately none of my boards have that port. https://reference.digilentinc.com/reference/pmod/pmodsf/start#example_projects Do you have any idea and/or suggestion how to bypass that usb controller in order to directly interact with the memory? Thank you in advance for your help! Regards, H
  11. Thank you Dan! I will try to follow your advice and let you know if I face any problems! Regards, H
  12. Dear Digilent, I have a simple design on a BASYS3, which contains a MICROBLAZE, a LED and two PUSH BUTTONS. I can control how fast the LED is blinking by pressing the PUSH BUTTONS. The BITSTREAM of that design is stored in a non-volatile serial Flash device, which is attached to the ARTIX-7 FPGA using a dedicated quad-mode (x4) SPI bus. When the system starts, the contents of the flash memory are read and the FPGA is configured normally. I would like to be able to memorize the latest configuration of the PUSH BUTTONS in a non-volatile memory, so that the system at startup can use that configuration. In other words, I would like to allow the user, the option to write in a non-volatile memory, the latest configuration of the push buttons, without having to change the BITSTREAM all the time. Something likes partitioning non-volatile memory into two sections: 1- One section will be to store the BITSTREAM for configuration during system startup. 2- The other section will be to allow the user to read, modify (write) and save parameters for the next startup. Is it possible to do this with the BASYS3? If so, could you please advise me how to do it? If not, what kind of system would be needed to achieve this? Thank you in advance for any suggestions and advices. Regards, H
  13. Hi! Could somebody answer my questions, please? Thank you. Kind regards, H.
  14. Dear Digilent, I would like to know why you do not design Pmod ADC and PMOD DAC with a sampling rates higher than 2 MS/s? Is it due to the limitation of the serial protocol? Or the number of wires? Or just for something else? I am asking that question because I am interested to PMODs ADC/DAC, running at a sampling rate higher than 2 MS/s. Thank you. Kind regards, Herve
  15. Dear Bianca, Thank you for your answer. Can I know why the Gerber files and the PCB files are not for public? In case I am still interested to those files for educational and training, is there any protocol that I should follow? Thank you. Kind Regards, Herve
  16. Dear Digilent, I have one more question: The PDF schematic of the PCB (https://reference.digilentinc.com/basys3/basys3) do not have the sheet number 4. Could you please update it and load the complete file with all sheets? I am looking forward to hearing from you. Thank you!
  17. Hello! We recently purchased the Digilent Basys3 Artix-7 35T Device. We are looking for the "Gerber" files of that Device together with the project file "project.PrjPCB"? Thank you.
  18. Hi! Once again thank you for your helpful explanations. I have more questions related to the same topic: 1- Do you have any tutorial or example about how to sample a signal with aliasing and deduce what the original signal must have looked like ? 2- Could you please suggest me some Digilent FMC cards (ADC and DAC) that I could use to sample and rebuild a 1 MHz analog input signal ? 3- Do you any idea about the price of those FMCs (ADC and DAC) ? Thanks. Regards, Herve
  19. Hi tom21091! Thank you for your investigations. I really appreciate your help I believe that the parallel connection between the LED and the Pmods pins on the ZC702 is at the origin of the physical limitations. However, I cannot cut the pin on the transistor otherwise I will lose the guarantee and won't be able to exchange that board anymore. Thanks again and keep in touch! Regards, Herve
  20. Hi! I have to sample a 1 MHz Analog input Signal, then do some computation and send the result to a digital to analog converter. I would like to do this with digilent Pmods ( ADC and DAC) but I have to decide first which of the digilent Pmods will allow me to sample and rebuild a 1 MHz analog signal. Could you please advise me some of your Pmods that might fit for my application? What about Pmod AD1 and Pmod DA2/DA3? Thank you! Herve
  21. Hi Tom21091, I already checked that forum before but it doesn't explain how to disconnect the Gates of the FETs connected to the LEDs (Assuming that this is related to the problem we are facing). Did you try to run the design that I sent you on your ZC702 in the office? Did you get anything? Thank you. Herve
  22. Hello Tom21091! I am using the ZC702 evaluation board featuring the XC7Z020 CLG484 -1 AP SoC. http://www.xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html#hardware
  23. @JColvin: Thank you so much! @tom21091: Please find attached the project files (The top module is AD1C_DAC2.v, MYIP.vhd is a submodule inside AD1C_DAC2, ADC1_DAC2.ucf is the constraint file). Thanks again and let me know. Regards, Herve AD1C_DAC2.v ADC1_DAC2.ucf MYIP.vhd
  24. Hello tom21091! Do you have news about your investigations? Regards, Herve