Ahmed Alfadhel

Question: NN activation functions

By Ahmed Alfadhel, June 12, 2021 in Add-on Boards

• Has best answer

Question: Visualizing 5 kHz sine wave by Pmod DA3

By Ahmed Alfadhel, April 17, 2019 in Add-on Boards

• Has best answer

• pmod da3
• sine wave

Question: Does it possible to implement Python code on ARTY 7 board using Vivado HLS?

By Ahmed Alfadhel, January 30, 2020 in FPGA

• Has best answer

• arty 7
• python
• (and 1 more)

  Tagged with:

  • arty 7
  • python
  • vivado hls

Question: Verilog

By Ahmed Alfadhel, October 13, 2019 in FPGA

• Has best answer

• verilog

Question: Verilog Simulator

By Ahmed Alfadhel, October 15, 2019 in FPGA

• Awaiting best answer

• verilog

Question: Pmod DA3 clocking 1 2

By Ahmed Alfadhel, March 7, 2019 in FPGA

• Has best answer

• pmod da3

Question: Enevlope Detection using FPGA board

By Ahmed Alfadhel, July 24, 2019 in FPGA

• Awaiting best answer

• envelope detection

Question: Visualizing FIR filter output on oscilloscope

By Ahmed Alfadhel, June 28, 2019 in FPGA

• Awaiting best answer

• pmodda3
• fir

Question: IIR compiler

By Ahmed Alfadhel, June 26, 2019 in FPGA

• Has best answer

• iir

Question: PMOD CLP

By Ahmed Alfadhel, June 23, 2019 in Add-on Boards

• Has best answer

Question: FIR compiler 7.2 stopband

By Ahmed Alfadhel, June 14, 2019 in FPGA

• Awaiting best answer

• fir

Question: Selecting FIR filter architecture

By Ahmed Alfadhel, June 17, 2019 in FPGA

• Awaiting best answer

• fir

Question: Noisy Output from FIR Compiler

By Ahmed Alfadhel, June 13, 2019 in FPGA

• Awaiting best answer

• fir

Question: FIR compiler Amplitude

By Ahmed Alfadhel, June 4, 2019 in FPGA

• Awaiting best answer

• fir compiler

Question: Bit error rate (BER) calculations

By Ahmed Alfadhel, May 28, 2019 in Test and Measurement

• Awaiting best answer

• ber

Question: Increasing the clock frequency to 260 MHz

By Ahmed Alfadhel, May 18, 2019 in FPGA

• Awaiting best answer

• clock

Question: how to get low clocking rate by ARTY 7 ?

By Ahmed Alfadhel, April 24, 2019 in FPGA

• Has best answer

Question: Pmod DA3 Pinout

By Ahmed Alfadhel, March 9, 2019 in FPGA

• Has best answer

• pmod da3

Question: A0 -A5 Constraints in Arty 7

By Ahmed Alfadhel, March 8, 2019 in FPGA

• Awaiting best answer

• constrains

Question:  DIFF_SSTL15 to TMDS_33

By Ahmed Alfadhel, March 7, 2019 in FPGA

• Awaiting best answer

• conflicting vcc voltages

Question: Conflicting Voltages in Bank Arty-A7

By Ahmed Alfadhel, March 4, 2019 in FPGA

• Awaiting best answer

• rule violation
• error
• (and 2 more)

  Tagged with:

  • rule violation
  • error
  • bank
  • voltage

Question: No thing is appearing at Tera Term !

By Ahmed Alfadhel, February 27, 2019 in Digilent Microcontroller Boards (Retired)

• Has best answer

• tera term

source code Question: Source Code in SDK 1 2

By Ahmed Alfadhel, January 2, 2019 in FPGA

• Awaiting best answer

• sdk
• pmod da3

Question: How to visualize clock signal of ARTY 7 kit using oscilloscope?

By Ahmed Alfadhel, February 22, 2019 in FPGA

• Has best answer

• clock signal

Question: Read data form IOmodule

By Ahmed Alfadhel, February 10, 2019 in FPGA

• Awaiting best answer

• microblaze