Ahmed Alfadhel

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Everything posted by Ahmed Alfadhel

  1. Ahmed Alfadhel

    Verilog

    Hi @D@n, After I did my check on the different Verilog tutorials, I would like to inform you that your Verilog tutorails on zipcpu.com is the best suited for me. Since they are more tidy and also fill the gaps in other tutorials. Such as in your tutorial lsn-01, Verilog literals are discussed. But, I will not use Verilator , since it lacks to its own GUI and hard to carry out a regular test bench with it. I will use Vivado Simulator since I have an experience with it (I used it to make test benches by VHDL) and I haven't any issue with it. Thanks
  2. Hi @D@n, I read your article, and I didn't know how to install Verilog on Windows. So I installed Oracle VM then Kali Linux and then Verilator. However, when I came back to your lecture lsn-01 and tried to build the first design by using Verilator, an error exist when I carried out the commands in Terminal window (as shown in the 2nd attached picture). Pls, see the attached picture. Looking forward your help. Thanks
  3. Ahmed Alfadhel

    Verilog Simulator

    Hi @D@n Thanks for your replies to my questions . They are very helpful . I just want to know does it possible to download Verilator on Windows? If not possible , what are the available options for me to download a Verilog Simulator on Windows? Thanks.
  4. Ahmed Alfadhel

    Verilog

    Hi , I want to learn Verilog . What you suggest for me to start with ? Any recommended books , websites or online courses? Thanks
  5. Hi @hamster, I increased the width of the ports and the signals to 28 bits and the error is still existed ! I am looking forward your reply. Thanks.
  6. Hi , Thank u @hamster for your elaboration about Hilbert Transform. I modified your code to work with my design , as follow: --Hilbert Transformer library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity hilbert_transformer is Port ( clk : in STD_LOGIC; real_in : in STD_LOGIC_VECTOR (23 downto 0); real_out : out STD_LOGIC_VECTOR (24 downto 0) := (others => '0'); imag_out : out STD_LOGIC_VECTOR (24 downto 0) := (others => '0')); end hilbert_transformer; architecture Behavioral of hilbert_transformer is -- Constants are 2/(n * pi) * 512, for n of -7,-5,-3,-1,1,3,5,7 constant kernel0 : signed(real_in'length-1 downto 0) := to_signed( -47, real_in'length); constant kernel2 : signed(real_in'length-1 downto 0) := to_signed( -66, real_in'length); constant kernel4 : signed(real_in'length-1 downto 0) := to_signed(-109, real_in'length); constant kernel6 : signed(real_in'length-1 downto 0) := to_signed(-326, real_in'length); constant kernel8 : signed(real_in'length-1 downto 0) := to_signed( 326, real_in'length); constant kernel10 : signed(real_in'length-1 downto 0) := to_signed( 109, real_in'length); constant kernel12 : signed(real_in'length-1 downto 0) := to_signed( 66, real_in'length); constant kernel14 : signed(real_in'length-1 downto 0) := to_signed( 47, real_in'length); type a_delay is array (0 to 14) of signed(real_in'high downto 0); signal delay : a_delay := (others => (others => '0')); signal tap0 : signed(real_in'length+kernel0'length-1 downto 0) := (others => '0'); signal tap2 : signed(real_in'length+kernel2'length-1 downto 0) := (others => '0'); signal tap4 : signed(real_in'length+kernel4'length-1 downto 0) := (others => '0'); signal tap6 : signed(real_in'length+kernel6'length-1 downto 0) := (others => '0'); signal tap8 : signed(real_in'length+kernel8'length-1 downto 0) := (others => '0'); signal tap10 : signed(real_in'length+kernel10'length-1 downto 0) := (others => '0'); signal tap12 : signed(real_in'length+kernel12'length-1 downto 0) := (others => '0'); signal tap14 : signed(real_in'length+kernel14'length-1 downto 0) := (others => '0'); begin process(clk) variable imag_tmp : signed(real_in'length*2-1 downto 0); begin if rising_edge(clk) then real_out <= std_logic_vector(resize(delay(8),real_out'length)); -- deliberatly advanced by one due to latency imag_tmp := tap0 + tap2 + tap4 + tap6 + tap8 + tap10 + tap12 + tap14; imag_out <= std_logic_vector(imag_tmp(imag_tmp'high downto imag_tmp'high-imag_out'high)); tap0 <= delay(0) * kernel0; tap2 <= delay(2) * kernel2; tap4 <= delay(4) * kernel4; tap6 <= delay(6) * kernel6; tap8 <= delay(8) * kernel8; tap10 <= delay(10) * kernel10; tap12 <= delay(12) * kernel12; tap14 <= delay(14) * kernel14; -- Update the delay line delay(1 to 14) <= delay(0 to 13) ; delay(0) <= signed(real_in); end if; end process; end Behavioral; and -- magnitude IP library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity magnitude is Port ( clk : in std_logic; x_in : in std_logic_vector(24 downto 0); y_in : in std_logic_vector(24 downto 0); x_out : out std_logic_vector(24 downto 0) := (others => '0'); y_out : out std_logic_vector(24 downto 0) := (others => '0'); magnitude_out : out std_logic_vector(24 downto 0) := (others => '0') -- Accurate to 5 bits or so ); end magnitude; architecture Behavioral of magnitude is type a_x is array(0 to 5) of signed(x_in'high+1 downto 0); type a_y is array(0 to 5) of signed(y_in'high+1 downto 0); type a_x_delay is array(0 to 5) of std_logic_vector(x_in'high downto 0); type a_y_delay is array(0 to 5) of std_logic_vector(y_in'high downto 0); -- line 23 (error occured here) signal x : a_x(24 downto 0) := (others => (others => '0')); signal y : a_y(24 downto 0) := (others => (others => '0')); signal x_delay : a_x_delay(24 downto 0) := (others => (others => '0')); signal y_delay : a_y_delay(24 downto 0) := (others => (others => '0')); begin magnitude_out <= std_logic_vector(y(5)); x_out <= x_delay(x_delay'high); y_out <= y_delay(y_delay'high); process(clk) begin if rising_edge(clk) then if x(4) >= 0 then -- x(5) is not needed y(5) <= y(4) + x(4)(x(4)'high downto 4); else -- x(5) is not needed y(5) <= y(4) - x(4)(x(4)'high downto 4); end if; if x(3) >= 0 then x(4) <= x(3) - y(3)(y(3)'high downto 3); y(4) <= y(3) + x(3)(x(3)'high downto 3); else x(4) <= x(3) + y(3)(y(3)'high downto 3); y(4) <= y(3) - x(3)(x(3)'high downto 3); end if; if x(2) >= 0 then x(3) <= x(2) - y(2)(y(2)'high downto 2); y(3) <= y(2) + x(2)(x(2)'high downto 2); else x(3) <= x(2) + y(2)(y(2)'high downto 2); y(3) <= y(2) - x(2)(x(2)'high downto 2); end if; if x(1) >= 0 then x(2) <= x(1) - y(1)(y(1)'high downto 1); y(2) <= y(1) + x(1)(x(1)'high downto 1); else x(2) <= x(1) + y(1)(y(1)'high downto 1); y(2) <= y(1) - x(1)(x(1)'high downto 1); end if; if x(0) >= 0 then x(1) <= x(0) - y(0)(y(0)'high downto 0); y(1) <= y(0) + x(0)(x(0)'high downto 0); else x(1) <= x(0) + y(0)(y(0)'high downto 0); y(1) <= y(0) - x(0)(x(0)'high downto 0); end if; if y_in(y_in'high) = '1' then x(0) <= signed(x_in(x_in'high) & x_in); y(0) <= signed(to_signed(0,y_in'length+1)-signed(y_in)); else x(0) <= signed(x_in(x_in'high) & x_in); y(0) <= signed(y_in(y_in'high) & y_in); end if; -- Delay to output the inputs, so they are aligned with the magnitudes x_delay(1 to 5) <= x_delay(0 to 4); y_delay(1 to 5) <= y_delay(0 to 4); x_delay(0) <= x_in; y_delay(0) <= y_in; end if; end process; end Behavioral; and I used my own test bench : library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; use std.textio.all ; use ieee.std_logic_textio.all ; -- Entity entity FHSS_TX_Test_Bench_sim is end; -- Architecture architecture test of FHSS_TX_Test_Bench_sim is -- Our UART Transmitter Design Instantiation component FH_modem_wrapper port ( BFSK : out STD_LOGIC_VECTOR ( 7 downto 0 ); FH : out STD_LOGIC_VECTOR ( 7 downto 0 ); spreaded_signal : out STD_LOGIC_VECTOR ( 7 downto 0 ); despreaded : out STD_LOGIC_VECTOR ( 7 downto 0 ); IF_BPF : out STD_LOGIC_VECTOR (23 downto 0); x : out STD_LOGIC_VECTOR ( 24 downto 0 ); y : out STD_LOGIC_VECTOR ( 24 downto 0 ); mag_out : out STD_LOGIC_VECTOR ( 24 downto 0 ); absolute2 : out STD_LOGIC_VECTOR ( 23 downto 0 ); envelop : out STD_LOGIC_VECTOR ( 47 downto 0 ); sys_clock : in STD_LOGIC; reset : in STD_LOGIC ); end component; -- Simulation signals signal clk_sim : std_logic := '0'; signal reset : std_logic := '1'; signal BFSK : std_logic_vector(7 downto 0); signal FH : std_logic_vector(7 downto 0); signal spreaded_signal : std_logic_vector(7 downto 0); signal despreaded : std_logic_vector(7 downto 0); signal IF_BPF : std_logic_vector(23 downto 0); signal x : std_logic_vector(24 downto 0); signal y : std_logic_vector(24 downto 0); signal mag_out : std_logic_vector(24 downto 0); signal absolute2 : STD_LOGIC_VECTOR ( 23 downto 0 ); signal envelop : STD_LOGIC_VECTOR ( 47 downto 0 ); begin -- UART Transmitter port mapping dev_to_test: FH_modem_wrapper port map(BFSK, FH, spreaded_signal, despreaded, IF_BPF, x, y, mag_out, absolute2,envelop, clk_sim, reset ); -- Simulate the input clock to our design clk_proc : process begin wait for 5 ns; clk_sim <= not clk_sim; end process clk_proc; end test; But when I run the simulation , I get on this error: [VRFC 10-9] a_x already imposes an index constraint ["D:/Users/dell/Complex_Envelop_detector_15kHzIF_Fig2/modem/modem.ip_user_files/bd/FH_modem/ipshared/e786/sim/magnitude.vhd":23] I had pointed to the line 23 by a comment before it. How to solve this error? I am looking forward your reply. Thanks.
  7. Hi @hamster, @D@n, @xc6lx45 Thank you for your replies. I used two stage of modulation. As I mentioned above : This will lead to a modulated signal similar to AM signal , since the MFSK (frequency hops) are higher than the BFSK frequency. Kindly, see the attached pictures. The second picture is the transmitted signal (modulated signal). Any more notes, I am really appreciating them. @hamster, I don't understand why you embedded C code here! Where I can use it? Thanks.
  8. Hi , I am using ARTY 7, with Pmod DA3 . I generated frequency hops (FH) signal then I used these hops to modulate a BFSK (Binary Frequency Shift Keying) signal . Currently I am trying to recover the envelope of the BFSK signal. But I don't now how to do that by using the FPGA board. I did a google search , and I found some people are using Hilbert Transform (HT) to recover the envelope of a modulated signal. But this technique (HT) seems need more illustration about how to implement it by FPGA. The question is : how to detect the envelop of a modulated signal using an FPGA board? Kindly, see the attached two pictures; the first one is illustrating envelop detection process, and the second one is illustrating the block diagram of the system that I built on my FPGA . Thanks.
  9. @D@n, I have to sample the FIR data in 8 bits packets (Array of bytes) each time since is declared in xspi.c library as follow: int XSpi_Transfer(XSpi *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, unsigned int ByteCount) { u32 ControlReg; u32 GlobalIntrReg; u32 StatusReg; u32 Data = 0; u8 DataWidth; /* * The RecvBufPtr argument can be NULL. */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(SendBufPtr != NULL); Xil_AssertNonvoid(ByteCount > 0); Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); if (InstancePtr->IsStarted != XIL_COMPONENT_IS_STARTED) { return XST_DEVICE_IS_STOPPED; . . . . . (long code) Thanks.
  10. Hi @D@n, I did a two 's complement for each byte to be written to the Pmod DA3. As shown below: void DA3_WriteSpi(PmodDA3 *InstancePtr, u32 wData) { u8 bytearray[4]; // u32 wData it is the same tdata from fir bytearray[0] = ((wData & 0xFF) ^ (0x80)); bytearray[1] = (((wData & 0xFF00) >> 8 ) ^ (0x80)); bytearray[2] = (((wData & 0xFF0000) >> 16) ^ (0x80)); bytearray[3] = (((wData & 0xFF000000) >> 24) ^ (0x80)); XSpi_Transfer(&InstancePtr->DA3Spi, bytearray, NULL, sizeof(bytearray)); } ___________________________________________________ Thanks
  11. Hi , Previously, I succeeded to generate a sinewave and visualize it on oscilloscope as shown in this post. Then I learnt how to use FIR filter compiler as shown in this post. Now, I am trying to visualize the FIR output on oscilloscope. I generated the bit stream file for the intended design (screenshot attached) then I viewed the output using Pmod DA3 , then the surprise it was only 1s and 0s ! as shown in the second attached picture. Note : I tried to pass 16 kHz by the FIR. I need your help about this issue. Any ideas about the reasons that make the output digital even when I am using DAC (Pmod DA3) ? Thanks.
  12. Ahmed Alfadhel

    IIR compiler

    Hi , Simple Question : Why there is no IIR compiler in Vivado IDE? Why there is only FIR compiler? In fact, I am using ARTY 7 baord and facing the DSP slices limitation when using FIR filters (I need to use 7 filters in my design). Thanks.
  13. Ahmed Alfadhel

    PMOD CLP

    Hi , I didn't find the dedicated libraries for PMOD CLP IP core in Vivado library for Pmods ! Kindly, if someone have an experience with it , I hope from you to instruct me about how to use it. Thanks.
  14. Hi @xc6lx45, Previously, I viewed the impulse response on TFilter website. I attached a snapshot for it. Thanks.
  15. Hi @xc6lx45, @D@n, @hamster I built my own IP core for impulse generation. And I run the simulation test. I don't know how to view the impulse response !? Code : ---------------------------------------------------------------------------------- -- Engineer: Ahmed Alfadhel -- -- Create Date: 06/19/2019 09:46:48 PM -- Design Name: -- Module Name: Impulse - Behavioral -- Project Name: -- Target Devices: -- Tool Versions: -- Description: Clk = 200 MHz -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Impulse is Port ( clk : in STD_LOGIC; impulse_data : out STD_LOGIC_VECTOR (7 downto 0); Valid : out STD_LOGIC; Ready : in STD_LOGIC); end Impulse; architecture Behavioral of Impulse is signal o_impulse : std_logic_vector(7 downto 0) := X"00"; signal s_Valid : std_logic := '0'; constant maxcount : integer := 4000; begin impulse_data <= o_impulse; Valid <= s_Valid; LFSR_proc: process(clk) variable counter: unsigned(14 downto 0) := to_unsigned(0, 15); begin if(rising_edge(clk)) then counter := counter +1; if (counter = maxcount) then o_impulse <= X"40"; s_Valid <= '1'; counter := (others => '0'); else o_impulse <= X"00"; s_Valid <= '0'; end if; end if; end process LFSR_proc; end Behavioral; ________________________________________________________________________________ Kindly ,see the attached snapshots for simulation. The second snapshot is just a zoom out for the first one.
  16. Hi @xc6lx45, Kindly, What this attribute stands for? I looked through Circuit Design with VHDL book for Pedroni, but I didn't find a similar thing like this attribute . thanks
  17. Hi , I am using a signal of a frequency of 16 kHz sinewave, and the sampling frequency (Fs) is 48 kHz in my design, and I want to test it with FIR filter compiler 7.2. I built simple design (first attached picture), consists form a DDS compiler and FIR compiler. Then I imported the FIR coeffiecents from Tfilter tool. However, the FIR filter was passing even the frequncies in the stopband, as illustrated in this discussion thread. I looked through UG073, and I found figure 5.1 (second attached picture) shows the sampling frequcies lower than 0.5 MHz is processed by Sequnctial FIR filter architechure. While the FIR compiler options are only providing Parallel FIR filter architecure (Systolic Multiply Accumulate) as shown in the third attached picture. Is there any way to change the filter architecture in FIR compiler 7.2 ? If only this architechture (Systolic) is available, what I can do to stop the frequencies in the stopband from passing the FIR filter? Thanks.
  18. Hi @xc6lx45, I think I have to build my own IP core (impulse generator), in order to do the the impulse test . Does that is right? Thanks.
  19. Hi , According to the Tfilter tool parameters (first attached picture) and the frequency response of FIR IP core (second attached picture) the passband is : 16 kHz to 17 kHz, and stopband1 is: 0 to 15.5 kHz and stopband2 is: 17.5 kHz to 24 kHz . I tested (simulated) the filter with 16 kHz , 24 kHz , 64 kHz, 500 kHz, and 1000 kHz. The simulation results are shown below respectively. 16 kHz 24 kHz 64 kHz 500 kHz 1000 kHz I noticed there is no attenuation in each of 24 kHz, 64 kHz !!! While 500 kHz, 1000 kHz appeared attenuated. The question is: why the FIR filter doesn't attenuate the frequencies that are located in the stopband? Note :in each attached picture the first sinewave is the input to the FIR Filter, while the second one is the output (filtered). Thanks.
  20. Hi @D@n, Kindly, Open this link from Xilinx Forum (Another Discussion Thread about this topic). I removed part of the noise. Any notes I really appreciate them. Thanks
  21. Hi , I am trying to impelement FIR compilers in my system design. I depended on TFilter (http://t-filter.engineerjs.com/) in my design for the FIR filter. The filter parameters (frequency response) are shown in the first attached picture. The interface connections between the DDS compiler (16 kHz oscillator) the FIR compiler are shown the second attached picture. After I imported the coefficients file in FIR IP core, then I run the a simulation to check the output of the FIR filter. The third attached picture shows a noisy output for this filter ! The FIR filter type is "Single Rate", the fourth attached picture shows the frequency response for the imported coefficients inside the FIR compiler. Plz, how to fix the output signal to become smooth like the input? Thanks.
  22. Hi @xc6lx45, I am grateful for your helpful explanations. Could you pls, tell me why there is an error when I set the "Quantization" to any other option other than "Integer Coefficients" ? Kindly, see the attached picture.
  23. Hi @xc6lx45, Could you please, tell me from which tab to reach the decimal point position settings? I checked all the tabs, but I couldn't find it. Kindly, see the attached picture. thank you for your reply.
  24. Hi, I used FIR filter for my system, and I imported the coefficients form Matlab using FDA tool. In matlab (FDA tool), I set the stop band to - 80 dB and the pass band to 0 dB, as indicated in the first attached picture. But when I opened the coefficients file in Vivado by FIR IP block and checking the frequency response of the filter, the situation was different, as shown in the second attached picture. In fact, the stop band is 50 dB ! and pass band is 125 dB ! I think these are wrong values. How to modify these values in order to be the same as of FDA matlab tool ? Thanks.
  25. Hi, I used Vivado IDE to design a transmitter and a receiver. In case I implemented my the transmitter on FPGA board and the receiver on another FPGA board (ARTY 7), how to calculate BER value for this transceiver? Thanks.