Ahmed Alfadhel

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About Ahmed Alfadhel

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  1. Hi @kwilber, It seems that part of your DIN signal (MOSI) is also under high level of ~CS (Enable)! as shown in the first attached picture. I think that mean part of your data is unread by PMod DA3. I openned your design using Vivado 2018.2 , so just I upgraded the IPs. I didn't use your design or code since it is different from my design, but I took some notes from your design such as you are using different clocks signals for ext_spi_clk and s_axi_aclk . I attached a snapshot for my design. Thanks.
  2. Hi @Billel, It is possible to use DDS compiler with Microblaze for the generation of sin and cos waveforms, with aid of Matlab System Generator. Kind Regards.
  3. Hi @kwilber, Could you visualize in dual mode each of ~CS signal and DIN signal, in order to know if you have the problem I have : In fact, I followed your instructions in the PM, but I still with same problem ! Thanks.
  4. Hi @kwilber, I tested your simplified version of DA3_WriteSpi function. But I found part of DIN (Data) signal is under high level of ~CS signal as shown in the second attached picture. Which is meaning part of data signal is unread by the PMOD DA3. The first attached picture is showing the measured Analog signal by SMA connector. It is supposed to be 1 kHz sinewave but it is not. Even the shap is still far from regular sinewave. Back again to my code, I found the variable Hops_reading is defined as u32. So, I did some changes to my code as follow: u32 Hops_reading_32; while(delay_count < 5000000) { Hops_reading_32 = XIOModule_DiscreteRead(&gpi, 1); // Perform Hop Reading u16 Hops_reading_16[2]; Hops_reading_16[0] = ((Hops_reading_32 & (0xFFFF0000)) >> 16); Hops_reading_16[1] = (Hops_reading_32 & (0xFFFF)); int i; for (i=0;i<=1;i++) { DA3_WriteSpi(&myDevice, Hops_reading_16[i]); } delay_count++; } After that I re-debugged again my design, but the main problem of "part of DIN (Data) signal is under high level of ~CS signal" is still existed ! as shown in the third attached picture. The fourth attached picture is showing the analog output from SMA connector. Also, it is supposed to be 1 kHz sinewave signal. But still far away from the regular sinewave ! I am looking forward your help. Thanks.
  5. Hi @JColvin, Could you tell me how to setup ~LDAC signal? Because as the attached picture shows it is not right signal. Thanks .
  6. Hi @jpeyron, In the attached photo, I am visualizing each of ~CS signal on channel one and ~LDAC on channel two. Why ~LDAC is always is 0 ? According the manual it must be 0 only during ~CS is 1 . Thanks in advance.
  7. Hi @kwilber, After the amendments. I got 16 clocks. But with silent part (not used time).
  8. Hi @kwilber, Thank you again for your perfect analyzing of my code. I made an amendment on the code. I made the the pointer *wData size is u8 again (the original size that I found). I am now thinking for a substitute to the parameter sizeof( ) . Does it possible to pass 1 , since the pointer *wData is u8 ? void DA3_WriteSpi(PmodDA3 *InstancePtr, u8 reg, u8 *wData, int nData) { // As requested by documentation, first byte contains: // bit 7 = 0 because is a write operation // bit 6 = 1 if more than one bytes is written, 0 if a single byte is written // bits 5-0 - the address u8 bytearray[nData+1]; bytearray[0] = ((nData>1) ? 0x40: 0) | (reg&0x3F); memcpy(&bytearray[1],wData, nData);//Copy write commands over to bytearray XSpi_Transfer(&InstancePtr->DA3Spi, bytearray, 0, nData+1); } Thanks in advance.
  9. Hi @jpeyron, It seems the .XCI file is locked and cannot be accessed ! See the attached picture. Looking froward your reply. Thanks in advance.
  10. Hi @kwilber, Thank you for your time that you spent to analyze my code and follow up with me my issue. I thought that the sizeof(Hops_reading) = 32, since it is u32 . I tried to check that using Print function with Tera Term, int size_hop; size_hop = sizeof(Hops_reading); print(size_hop); however, I got 'p' on Teram Term ! Why? Thanks for your support.
  11. Hi @jpeyron, According to the selection of 50 MHz as a clock signal for both ext_spi_clk and s_axi_aclk , then we have synchromous clocking for these two signals. Then the value of Async_Clk must be set to 0 . But I found in PmodDA3_axi_quad_spi_0_0.xci the property Async_Clk was set to 1 (not a default value !) on line 83 and 106 . Looking forward your reply . Thanks in advance.
  12. Hi @jpeyron, I found in PmodDA3_axi_quad_spi_0_0.xci the property C_NUM_TRANSFER_BITS ( Transaction Width) was set to 8 bits (the default value) on line 90 and 112. I think it must be set to 16 bits, since the Pmod DA3 its resolution is 16 bits. Looking forward your reply. Thanks in advance.
  13. Hi @jpeyron, did you test this Pmod (DA3) with the above piece of code previously? Or I am going the first one to test it using the IP core you gave me ? I want to know what is I am doing . Working with a validated third IP core or I am just testing some IP core that was built roughly ? Thanks.
  14. Hi @kwilber, Do you mean I have to build my own IP core for Pmod DA3 using Vivado IDE , like that of Hamester ?
  15. Hi @jpeyron, Kindly find the attached files. Kind Regards. testperiph.c PmodDA3.h PmodDA3.c