Ahmed Alfadhel

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About Ahmed Alfadhel

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  1. Hi , Does it possible to implement Python code on ARTY 7 board using Vivado HLS? If it is not, why it is possible with PYNQ board? Thanks
  2. Ahmed Alfadhel

    Verilog

    Hi @[email protected], After I did my check on the different Verilog tutorials, I would like to inform you that your Verilog tutorails on zipcpu.com is the best suited for me. Since they are more tidy and also fill the gaps in other tutorials. Such as in your tutorial lsn-01, Verilog literals are discussed. But, I will not use Verilator , since it lacks to its own GUI and hard to carry out a regular test bench with it. I will use Vivado Simulator since I have an experience with it (I used it to make test benches by VHDL) and I haven't any issue with it. Thanks
  3. Hi @[email protected], I read your article, and I didn't know how to install Verilog on Windows. So I installed Oracle VM then Kali Linux and then Verilator. However, when I came back to your lecture lsn-01 and tried to build the first design by using Verilator, an error exist when I carried out the commands in Terminal window (as shown in the 2nd attached picture). Pls, see the attached picture. Looking forward your help. Thanks
  4. Hi @[email protected] Thanks for your replies to my questions . They are very helpful . I just want to know does it possible to download Verilator on Windows? If not possible , what are the available options for me to download a Verilog Simulator on Windows? Thanks.
  5. Ahmed Alfadhel

    Verilog

    Hi , I want to learn Verilog . What you suggest for me to start with ? Any recommended books , websites or online courses? Thanks
  6. Hi @hamster, I increased the width of the ports and the signals to 28 bits and the error is still existed ! I am looking forward your reply. Thanks.
  7. Hi , Thank u @hamster for your elaboration about Hilbert Transform. I modified your code to work with my design , as follow: --Hilbert Transformer library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity hilbert_transformer is Port ( clk : in STD_LOGIC; real_in : in STD_LOGIC_VECTOR (23 downto 0); real_out : out STD_LOGIC_VECTOR (24 downto 0) := (others => '0'); imag_out : out STD_LOGIC_VECTOR (24 downto 0) := (others => '0')); end hilbert_transformer; architecture Behavioral of hilbert_transformer is -- Con
  8. Hi @hamster, @[email protected], @xc6lx45 Thank you for your replies. I used two stage of modulation. As I mentioned above : This will lead to a modulated signal similar to AM signal , since the MFSK (frequency hops) are higher than the BFSK frequency. Kindly, see the attached pictures. The second picture is the transmitted signal (modulated signal). Any more notes, I am really appreciating them. @hamster, I don't understand why you embedded C code here! Where I can use it? Thanks.
  9. Hi , I am using ARTY 7, with Pmod DA3 . I generated frequency hops (FH) signal then I used these hops to modulate a BFSK (Binary Frequency Shift Keying) signal . Currently I am trying to recover the envelope of the BFSK signal. But I don't now how to do that by using the FPGA board. I did a google search , and I found some people are using Hilbert Transform (HT) to recover the envelope of a modulated signal. But this technique (HT) seems need more illustration about how to implement it by FPGA. The question is : how to detect the envelop of a modulated signal using an
  10. @[email protected], I have to sample the FIR data in 8 bits packets (Array of bytes) each time since is declared in xspi.c library as follow: int XSpi_Transfer(XSpi *InstancePtr, u8 *SendBufPtr, u8 *RecvBufPtr, unsigned int ByteCount) { u32 ControlReg; u32 GlobalIntrReg; u32 StatusReg; u32 Data = 0; u8 DataWidth; /* * The RecvBufPtr argument can be NULL. */ Xil_AssertNonvoid(InstancePtr != NULL); Xil_AssertNonvoid(SendBufPtr != NULL); Xil_AssertNonvoid(ByteCount > 0); Xil_AssertNonvoid(InstanceP
  11. Hi @[email protected], I did a two 's complement for each byte to be written to the Pmod DA3. As shown below: void DA3_WriteSpi(PmodDA3 *InstancePtr, u32 wData) { u8 bytearray[4]; // u32 wData it is the same tdata from fir bytearray[0] = ((wData & 0xFF) ^ (0x80)); bytearray[1] = (((wData & 0xFF00) >> 8 ) ^ (0x80)); bytearray[2] = (((wData & 0xFF0000) >> 16) ^ (0x80));
  12. Hi , Previously, I succeeded to generate a sinewave and visualize it on oscilloscope as shown in this post. Then I learnt how to use FIR filter compiler as shown in this post. Now, I am trying to visualize the FIR output on oscilloscope. I generated the bit stream file for the intended design (screenshot attached) then I viewed the output using Pmod DA3 , then the surprise it was only 1s and 0s ! as shown in the second attached picture. Note : I tried to pass 16 kHz by the FIR. I need your help about this issue. Any ideas about the reasons that make the output digital eve
  13. Ahmed Alfadhel

    IIR compiler

    Hi , Simple Question : Why there is no IIR compiler in Vivado IDE? Why there is only FIR compiler? In fact, I am using ARTY 7 baord and facing the DSP slices limitation when using FIR filters (I need to use 7 filters in my design). Thanks.
  14. Hi , I didn't find the dedicated libraries for PMOD CLP IP core in Vivado library for Pmods ! Kindly, if someone have an experience with it , I hope from you to instruct me about how to use it. Thanks.
  15. Hi @xc6lx45, Previously, I viewed the impulse response on TFilter website. I attached a snapshot for it. Thanks.