Ahmed Alfadhel

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  1. Hi , I am using Arty 7 kit to implement my design. At first I used a clock frequency of 130 MHz, and the timing was "met" . Then I increased the clock the clock frequency to 260 MHz , but the timing constraints were "not met" . Pls, see the attached picture. I read about the issue and I found myself I have to do some floorplanning for my design. How to do floorplanning? What is the first step that I have to do with floorplanning ? Thanks.
  2. Thank you @zygot for your effective notes. Now, my LFSR is working at 8 kHz according to Vivado simulator and according to the run on ARTY 7. Kind Regards.
  3. Hi Mr. @zygot, I added enable signal (i_en) , which is controlled by a counter. As shown in my code below: -- Library's library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.numeric_std.all; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity LFSR3 is Port ( i_clk : in std_logic; o_lsfr : out std_logic_vector (2 downto 0) -- i_en : in std_logic ); end LFSR3; architecture Behavioral of LFSR3 is signal i_en : std_logic := '1'; signal r_lfsr : std_logic_vector(2 downto 0) := "100"; constant maxcount : integer := 625; signal counter : unsigned(9 downto 0) := to_unsigned(0, 10); begin o_lsfr <= r_lfsr; LFSR_proc: process(i_clk) begin counter <= (others => '0'); i_en <= not i_en; if (i_en = '1') then if(rising_edge(i_clk)) then r_lfsr(2) <= r_lfsr(0) xor r_lfsr(1); r_lfsr(1) <= r_lfsr(2); r_lfsr(0) <= r_lfsr(1); end if; else -- line 75 (the error) freq_8kHz: while (counter <= maxcount) loop counter <= counter + 1; end loop freq_8kHz; end if; end process LFSR_proc; end Behavioral; And , when I run synthesize, an error appeared : "[Synth 8-3380] loop condition does not converge after 2000 iterations ["d:/Users/dell/Vivado_projects/LFSR2/LFSR2.srcs/sources_1/bd/LFSR/ipshared/4f95/src/LFSR3.vhd:75]" I have pointed to the error location in my code (line 75) . So plz , could you tell me why my loop seems to be infinite (does not converge) !? Thanks.
  4. Hi , I need to use 8 kHz as a clock signal for my LFSR IP core in my block design. But this low rate can not be implemented in ARTY 7 , as shown in the attached picture ! What are the other choices I have in order to achieve the output of LFSR at the low rate that I want ? I read about delays in FPGA , but I found delays are not synthesized in FPGA ! Looking for your help, Thanks
  5. Hi @D@n Thank you for your perfect analyzing and solution to my issue . I just toggled the MSB in each written Byte and I got the sinewave finally. However, I wondered , since in the data sheets (AD5541A , AD7303) is mentioned I have to use operation amplifier in order to get a bipolar signal ! Thanks again.
  6. Hi , I am using DDS IP core to visualize a 5 kHz sine wave signal. At first I simulated the IP core using Vivado simulator . I used 25 MHz clock signal. I got a sine wave signal as shown in the first attached picture. When I changed the Radix from "signed data type" to "unsigned data type" the sine wave will be like in the second attached picture. And when I implemented my design on my ARTY 7 , and connected the output of Pmod DA3 to the oscilloscope , I got a signal similar to that in the second attached picture ! As shown in the third attached picture . I changed all the intended data types in my program from u16 to s16 but the no thing is changed ! Pls , I am looking forward your help. How to visualize a DDS sine wave properly using Pmod DA3 ? Thanks.
  7. Hi @tommienator, According to my basic understanding, if we increase the SCLK signal up to 50 MHz for Pmod DA3 module, the speed of the reconstruction process will be higher . Hence I believe DAC doesn't need to comply the Shannon's theory. Regards.
  8. Hi @kwilber, No. I used that came with Pmod DA3 . But, I changed the transaction width to 16-bits , and I commented out StatusReg = XSpi_GetStatusReg(InstancePtr) . Thanks
  9. Hi @kwilber; I used the same my design, but I modified my code to generate the sawtooth signal. as you did: u16 dacData = 0; while (1) { ++dacData; DA3_WriteSpi(&myDevice, dacData); } /* int i; for (i=0;i<=1;i++) { DA3_WriteSpi(&myDevice, Hops_reading_16[i]); }*/ And I succeeded to get 266 Hz Sawtooth signal. Are you got the same frequency? Back to my topic, I asked my self why I didn't get the sinwave ? And put the following answers: 1. Maybe I need to use "AXI GPIO" IP core instead of "IOModule" IP core in my system design. 2. Maybe the sinwave IP core (generated by Matlab System Generator) has improper value of "Explicit Sample Time" or "Simulink System Period". So, I will use Vivado simulator with to view my Sinewave. Thanks for your Help.
  10. Hi @kwilber, It seems that part of your DIN signal (MOSI) is also under high level of ~CS (Enable)! as shown in the first attached picture. I think that mean part of your data is unread by PMod DA3. I openned your design using Vivado 2018.2 , so just I upgraded the IPs. I didn't use your design or code since it is different from my design, but I took some notes from your design such as you are using different clocks signals for ext_spi_clk and s_axi_aclk . I attached a snapshot for my design. Thanks.
  11. Hi @Billel, It is possible to use DDS compiler with Microblaze for the generation of sin and cos waveforms, with aid of Matlab System Generator. Kind Regards.
  12. Hi @kwilber, Could you visualize in dual mode each of ~CS signal and DIN signal, in order to know if you have the problem I have : In fact, I followed your instructions in the PM, but I still with same problem ! Thanks.
  13. Hi @kwilber, I tested your simplified version of DA3_WriteSpi function. But I found part of DIN (Data) signal is under high level of ~CS signal as shown in the second attached picture. Which is meaning part of data signal is unread by the PMOD DA3. The first attached picture is showing the measured Analog signal by SMA connector. It is supposed to be 1 kHz sinewave but it is not. Even the shap is still far from regular sinewave. Back again to my code, I found the variable Hops_reading is defined as u32. So, I did some changes to my code as follow: u32 Hops_reading_32; while(delay_count < 5000000) { Hops_reading_32 = XIOModule_DiscreteRead(&gpi, 1); // Perform Hop Reading u16 Hops_reading_16[2]; Hops_reading_16[0] = ((Hops_reading_32 & (0xFFFF0000)) >> 16); Hops_reading_16[1] = (Hops_reading_32 & (0xFFFF)); int i; for (i=0;i<=1;i++) { DA3_WriteSpi(&myDevice, Hops_reading_16[i]); } delay_count++; } After that I re-debugged again my design, but the main problem of "part of DIN (Data) signal is under high level of ~CS signal" is still existed ! as shown in the third attached picture. The fourth attached picture is showing the analog output from SMA connector. Also, it is supposed to be 1 kHz sinewave signal. But still far away from the regular sinewave ! I am looking forward your help. Thanks.
  14. Hi @JColvin, Could you tell me how to setup ~LDAC signal? Because as the attached picture shows it is not right signal. Thanks .
  15. Hi @jpeyron, In the attached photo, I am visualizing each of ~CS signal on channel one and ~LDAC on channel two. Why ~LDAC is always is 0 ? According the manual it must be 0 only during ~CS is 1 . Thanks in advance.