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  1. Hi @jpeyron Actually, i checked almost all forum threads/posts about this topic. However, probably because of my lack of expertise I cannot solve the problem. If I create RTL module then i cannot figure out how to connect it to the AXI GPIO IP. Moreover, if I create an IP out of DA2RefCOmp, i dont figure out how to interface it with AXI. For example, I have a problem with connecting the CLK,RST and START inputs of DA2RefComp... I dont get where those inputs should be connected? I exactly know that the outputs should be routed to the external pins.. that is the easy part. Also, the DATA1 and DATA2 inputs are fed by my wave_generator. Any forum member's help on this problem is welcomed... my best regards, P.S. Do I need to design module i.e. DA2REFComp_Controller (IP or RTL module) to control the inputs/outputs of the DA2RefComp ? MD
  2. hey everyone, I am trying to generate different waveforms of analog signals using ZEDBOARD + PMODDA2. My previous question was about Pmod+zedboard. Then, I was able to simulate the example verilog code (pmod_da2_demo) and -after changing the constraint file (.xdc)- i generated the bitstream and programmed the FPGA on my ZEDBOARD. This example piece of code generates an 12-bit digital input to the DAC and the output is expected to be a triangular waveform whose output amplitude is in between around 1.5 and 2.5 Volts. When I checked the output on the o-scope i have obtained the following wave. However, I want use both PS and PL parts of the Zedboard. That is why i need a block design which will have ZYNQ7 PS + AXI interconnect + Processor System Reset etc plus my PMODDA2's reference component i.e. DA2RefComp. DA2RefComp's inputs are CLK,RST,DATA1,DATA2 and START. If I package DA2RefComp as an IP its GUI looks like as the following: The other option is to make an RTL module using the given DA2RefComp.vhd as shown below. I tried to make the RTL module to work with Zynq7 PS. Then reading from the forum's suggestions, I tried to make the following circuit. Using AXI GPIOs and AXI Int etc are connected automatically. The triangle_0 IP module just generates triangular wave. MY question is this connection below seems correct? I couldnt make it work, yet. Secondly, the CLK input of DA2RefComp requires 50 MHz input so should I divide the clock of the PS? What should I do with the RST input of DA2RefComp? Is it just good when connected to the other resets automatically?
  3. Thank you @kwilber. It was such an easy and silly question sorry for that : ) Now, since the simulation part is OK, i hope i will create an IP Core for it and then make it work! thanks again...
  4. I guess there is an error in wrapper.v file. The warning is "counter1 is already declared". I have no knowledge of verilog yet, how can I make it work?
  5. I have done all the things you say but still get the errors. Since it is only simulation, not synthesis and implementation i didnt arrange the zedboard_master.xdc constraints.. The errors are like follows: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/mehmet/Desktop/Pmod_DA2_Demo/Pmod_DA2_Demo.sim/sim_1/behav/xsim/xvlog.log' file for more information. ERROR: [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/mehmet/Desktop/Pmod_DA2_Demo/Pmod_DA2_Demo.sim/sim_1/behav/xsim/xvlog.log' file for more information. ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors. yes it seems like a compiation error. I use Vivado 2018.2 which runs on Windows 10 by the way.
  6. Still, the example demo project gives errors when I run Behavioral Simulation. I think @jpeyron might help because i guess he is the one created the testbench file. (Module Name: C:/Users/jpeyron/Desktop/xilinx software and files/RefCompIssue/test_bench.v) I will search for the following errors from Xilinx forums: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation. [USF-XSim-62] 'compile' step failed with error(s). Please check the Tcl console output or 'C:/Users/mehmet/Desktop/Pmod_DA2_Demo/Pmod_DA2_Demo.sim/sim_1/behav/xsim/xvlog.log' file for more information.
  7. hey kwilber, thank you for your helpful response. When i open the example project pmod_da2_demo.xpr, there is a "non-module file" DA2RefComp.vhd. When I put this .vhd file to the / Pmod_DA2_Demo\Pmod_DA2_Demo.srcs\sources_1\new, this demo project still do not work. Should I create an IP from DA2RefComp.vhd to make this demo work? have a nice day,
  8. Hey, Can I use Digilent's peripheral "Pmod DA2: Two 12-bit D/A Outputs" on zedboard ? If I check, this link, under Platforms Supported, ZedBoard is not listed. That makes me wonder if I still can use PMODDA2 and other Pmods on my zedboard? IF yes, i think we do not have an IP specificially created for PMODDA2...
  9. Hey again, Actually, I cannot see the following port under my device manager : "Select the COM port that corresponds to Silicon Labs CP210x USB to UART Bridge"
  10. Hi, Thank you John for your answer; I followed the instructions for the ZC702 board and tried to use the given .bit file for programming my ZEDBOARD. However, I receive a connection error "communication problem attempting the read from board" when I open AMS101 EValuator. So, should I change .bit file by re-building the hardware and re-generating it? regards,
  11. There doesn't seem to be a boot.bin file available for the zedboard + AMS101 evaulation eventhough the link below suggests there is.
  12. hey everyone, there are hardware & software setup files of AMS101 platform for some Xilinx's evaluation cards i.e. AC701, VC707, KC705 and ZC702. ( and Kits&xlnxdocumentid=UG960) However, I want to use AMS101 with ZedBoard but no idea how to set up. Any suggestions to do that? thanks
  13. Hey, I want to use ZedBoard's XADC for sampling an external analog signal. Only one channel (single channel) is sufficient for now. Therefore, I tried to use the dedicated inputs, namely VP/VN in bipolar mode. When I check USERGUIDE480's page 32, the following picture is given: 1) From this figure, I understand that VN port must be supplied with an external 0.5 DC voltage source. Am I correct? Can i get this 0.5V dc from the ZedBoard not using an external supply source? 2) Is it enough I only connect VP/VN pins of XADC header leaving out other pins unconnected? I mean should I connect AGND or DGND to ground? thanks in advance, mehmet PS: Sorry, I posted this question to the incorrect sub-forum.