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artvvb

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  1. Like
    artvvb got a reaction from Suprith in Reset package pin   
    Hi @Suprith
    The reset button on the Arty Z7 is not directly connected to the FPGA PL. Reviewing the schematic, the reset button, connected to the PS_RST net, triggers the PS side of the chip to reset and drives a reset on the CK_RST net, which is connected to the shield header reset pin. CK_RST is also connected to PS MIO12, however, this would not allow the PS to read a reset button press, since the upstream PS_RST will be applied.
    Reset signals within the FPGA can alternatively be driven by resets associated with the FCLKs.
    Thanks,
    Arthur
  2. Like
    artvvb reacted to bobvogt1961 in Equivalent for the WiFire Board, Rev C or D   
    Dear Arthur.
    Thanks for the reply.  I think I will complete my current project with the remaining WiFires I currently have. It is a nice product because it requires very basic programming (I use the Arduino IDE) and I have full confidence in the timing. It is also uniquely fast at 200 MHz.  Eventually I think I will bite the bullet and tackle the Raspberry Pi and its extra layers of operating system.  Thanks for the help.
    Bob
  3. Like
    artvvb got a reaction from jayasha in PCAM interfacing with zedboard   
    Hi @jayasha
    Yes, saving and processing images in software should be possible without modifications to the Vivado project.
    Thanks,
    Arthur
     
  4. Like
    artvvb got a reaction from Suprith in Arty z7-10 Pmod Package pins   
    Hi @Suprith
    The template XDC file for the Arty Z7-10 includes pin locations for the Pmod ports: https://github.com/Digilent/digilent-xdc/blob/master/Arty-Z7-10-Master.xdc. The schematics also include this information: https://files.digilent.com/resources/programmable-logic/arty-z7/arty-z7-d0-sch.PDF.
    Thanks,
    Arthur
  5. Like
    artvvb got a reaction from Suprith in Clock pin   
    Hi @Suprith
    Please review section 11, Clock Sources, of the Arty Z7 reference manual. When using Zynq PS software, FCLK pins inside of the chip can be used to clock FPGA fabric. Otherwise, the 125 MHz ethernet reference clock connected to H16 can be used.
    Thanks,
    Arthur
  6. Like
    artvvb reacted to bloggins666 in Arty Z7 Tutorial is out of sync with the vitis tool   
    Thanks Arthur, I've watched Whitney's videos and found them very good (although I don't like her cat's attitude, it's as if it doesn't care!). I'll check around and see if I can put the process together from bits and pieces of both of them.
    Thanks for all you help!!
    And now it's Pub time.
    Cheers!!
  7. Like
    artvvb reacted to wjwd in Zybo Z7 10 Baremetal Demo No Response   
    After trying to create my own version of a hello world, I finally figured it out. I had JP5 jumper installed on QSPI vice JTAG, I want to die. 
    For some reason my own hello world attempt threw me an error that was googlable enough to find the solution, but the demo version never gave me any sort of error. I'm having so much fun!
  8. Like
    artvvb got a reaction from jayasha in PCAM interfacing with zedboard   
    It depends on how you want to store data - if you want to grab and manipulate a frame in DDR, since the frames are already moving through DDR, this is possible with minor software changes only. You could also potentially dump image data out to an external application for further processing using UART (which would be slow) or ethernet. Writing an image from DDR to a file system, on, for example, an SD card, would also be possible - it requires having software access to the file system, which could potentially be done using additional libraries in baremetal, or by replicating the entire system using PetaLinux.
    Thanks,
    ARthur
  9. Like
    artvvb got a reaction from connoisseur_de_mimi in Zmod Faceplate mechanical drawings   
    Digilent doesn't currently provide mechanical dimensions for the faceplate directly, but I reached out internally to request them. If you haven't yet, please also review the Zmod and Eclypse mechanical diagrams, as they should help with some of the required dimensions:
    https://digilent.com/reference/programmable-logic/eclypse-z7/start#additional_resources https://digilent.com/reference/zmod/scope/start#additional_resources https://digilent.com/reference/zmod/awg/start#additional_resources Thanks,
    Arthur
  10. Like
    artvvb got a reaction from connoisseur_de_mimi in Zmod Faceplate mechanical drawings   
    Hi @connoisseur_de_mimi
    An STP file for the enclosure kit is now available here: https://files.digilent.com/resources/programmable-logic/eclypse/Eclypse_Z7_Enclosure.stp
    Thanks,
    Arthur
  11. Like
    artvvb reacted to rogermiranda1000 in How to exchange data between PL and PS?   
    I've been for two years in the same exact situation as you were. I checked some custom IPs tutorials to learn how to communicate with the AXI bus, and with the Vivado integrated tool turns out to be pretty easy.
    I've created a tutorial showing an example of the exact same thing you wanted: PS-PL USART data exchange. Check it on my GitHub.
    I hope that it will help other people, and I'm open to accept PR of code improvements from people more experienced that I am.
  12. Like
    artvvb reacted to Stefanski881 in DMA sample duplicates   
    I solved the problem. It wasnt any timing issue what so ever. The traitor was the packetizer all along. Basically my rvalid signal was delayed by one clock cycle which caused all the problems.
    Sorry for wasting your time, it was a very simple mistake, but still thank you for responding!
  13. Like
    artvvb reacted to connoisseur_de_mimi in Syzygy DNA for custom Pod   
    I dug a little deeper using the dpmutil library. SyzygyReadDNAHeader() called in dpmutilFEnum() reads 0xFF only from EEPROM. I2C communication appears to work correctly, at least the I2C HAL does not return any errors, which should also mean the firmware is running correctly. I have read out the EEPROM with avrdude, it matches the file created by syzygy-tools.py. Lots of dead ends.
    What solved this issue in the end was patching the syzygy-tools.py script to work with my programmer and using it to flash the Pod MCUs 😩 Vio is now set as defined in the dna json.
  14. Like
    artvvb reacted to davwamai in Transfer Buffer Address issue in DDR Streaming demo   
    Found it. It was an inconsistency (or rather a consistency in this case) in the definitions. main() was pulling the DMA_ID for the scope rather than the awg. The projects use the same definition identifier for their respective DMA_IDs. 
    Changing 
    #define DMA_ID XPAR_ZMODAWG_PORTB_MM2SDMATRANSFER_0_AXI_DMA_0_DEVICE_ID -> #define DMA_ID_AWG XPAR_ZMODAWG_PORTB_MM2SDMATRANSFER_0_AXI_DMA_0_DEVICE_ID and editing the file accordingly did the trick. 
  15. Like
    artvvb reacted to connoisseur_de_mimi in decutil for bare metal applications?   
    looking good, thanks :)

  16. Like
    artvvb got a reaction from connoisseur_de_mimi in decutil for bare metal applications?   
    Hi @connoisseur_de_mimi
    See example code here: https://github.com/Digilent/Eclypse-Z7-SW/blob/b42fb15a8ab4c52a38db2c15918cd7263e84f65e/src/calibration_reader/src/main.c
    Thanks,
    Arthur
  17. Like
    artvvb reacted to connoisseur_de_mimi in Eclypse-Z7: PMOD I2C   
    Thanks @artvvb, it worked! I also added the Pullup constraint, as suggested (its not needed as my I2C devices have pullups built in, but it should make debugging easier).
     
    my constraints are now
     
  18. Like
    artvvb got a reaction from connoisseur_de_mimi in Eclypse-Z7: PMOD I2C   
    Hi @connoisseur_de_mimi
    Yeah, the issue is likely that it's a differential buffer.
    Manual instantiation of the IO buffers isn't necessary. You could just make the entire I2C interface external and constrain the two pins. Vivado will automatically add tristate buffers as appropriate. You can also add pullups through an XDC file with "pullup true" constraints like here:
    Also, port names for the below screenshot would be "IIC_0_scl_io" and "IIC_0_sda_io".

    Thanks,
    Arthur
  19. Like
    artvvb got a reaction from shreyash in BootROM not found while make -f Makefile.e300artydevkit mcs   
    Responded over in another thread, but the gist is that we're unfortunately not able to help much. The SiFive repo that the guide depends on was archived back in 2021, so they may not be much help either. 
     
  20. Like
    artvvb got a reaction from shreyash in BootROM not found while make -f Makefile.e300artydevkit mcs   
    Hi @shreyash
    Unfortunately, we can't provide much support for this guide anymore - the sources it clones from were archived as read-only by the third party who created it some time ago. We're looking at either taking down the guide or strengthening the warnings at the top so that others don't run into the same issues you have.
    Apologies,
    Arthur
  21. Like
    artvvb reacted to Xband in TIMING #1 The clocks DcoClk_1 and DcoClk_0 are related (timed together) but they have no common primary clock.   
    @artvvb
    I have the hardware design loaded and a software SOC testing now.  Exciting progress!  Getting an XAXIDMA_Device_To_DMA transfer length failure now!  Progress!
    Thanks for your continuing support, sorry to have two separate threads on my issues going.
  22. Like
    artvvb got a reaction from silverdiamond in How do you limit number of printed decimal places in print statement in a scripts?   
    Hi @silverdiamond
    The following should work:
    WaveForms' Script Editor is based on JavaScript.
    Thanks,
    Arthur
  23. Like
    artvvb got a reaction from Xband in Eclypse 1410 ADC constraint file name mismatch issue, IO placement Infeasible   
    Posted a project  and some constraints over here: 
     
    Just means that you are trying to use the same location constraint for two different pins - more incorrect constraints. sADC_Sclk_1 should probably be at AA13.
  24. Like
    artvvb got a reaction from Xband in Eclypse 1410 ADC constraint file name mismatch issue, IO placement Infeasible   
    Hi @Xband
    The AXI port names in the list of unplaced ports make me think that you have the wrong top module. Please make sure that the block design HDL wrapper is set as the top module for your project in the sources pane. It should be bolded, like here:

    You can change which module is selected as the top module by right-clicking on the one you want and selecting "Set as Top".
    Thanks,
    Arthur
  25. Like
    artvvb got a reaction from Xband in Trying to modify the constraints file to accommodate 2 ADC 1410 modules, do not see how the schematic and baseline files match?   
    Please review your HDL wrapper module, and confirm that all port names in XDCs match names in the wrapper. The issue with the github source that you linked is that it is intended to be used with a script that reproduces part of a block design, which also finds and replaces all of the "nameHier" text in the XDC. It then has the correct names of ports, since it creates the ports in a known way, as long as ports aren't manually renamed later.

    Thanks,
    Arthur

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